Soon-Cheon Seo

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

Tantalum Nitride Films Grown by Inorganic Low Temperature Thermal Chemical Vapor Deposition Diffusion Barrier Properties in Copper Metallization

Key findings are presented from a systematic study which evaluated the performance of chemical vapor deposited (CVD) nitrogen-rich tantalum nitride (TaN x , x ∼ 1.8) films as a diffusion barrier in copper (Cu) based metallization schemes. For this purpose, 3800 A thick Cu films were grown by physical vapor deposition (PVD) on 550 A thick TaN x films which were deposited by low temperature (<425°C) thermal CVD (TCVD) using tantalum pentabromide (TaBr 5 ), ammonia, and hydrogen as coreactants. The resulting stacks were annealed in argon ambient at 450, 500, 550, and 650°C for 30 min each, along with similar PVD Cu/PVD TaN x bilayers of identical thickness. Both types of pre- and postannealed stacks were characterized by X-ray photoelectron spectroscopy, Auger electron spectroscopy, Rutherford backscattering spectrometry, nuclear reaction analysis for hydrogen profiling, X-ray diffraction, stack sheet resistance measurements, and Secco chemical treatment and etch-pit observation by scanning electron microscopy. The resulting findings showed that the PVD TaN x films provided an excellent barrier against Cu diffusion throughout the annealing window investigated. Altematively, the TCVD TaN x films exhibited similar stability up to 550°C. Barrier failure occurred, however, at temperatures between 550 and 600°C, as revealed by the formation of etch pits after Secco etch treatment. The failure of the TCVD TaN x films could not be attributed to bromine incorporation, given that residual bromine (∼0.5 atom %) in the TCVD TaN x films was highly stable against thermal diffusion in the temperature window investigated. Instead, the higher thermal stability of the PVD TaN x was attributed to differences in film microstructure and crystalline phase, or the location of excess nitrogen within the film matrix.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the worlds smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Extremely thin SOI (ETSOI) technology: Past, present, and future

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Copper contact metallization for 22 nm and beyond

We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate worlds smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Evaluation of Direct Cu Electroplating on Ru: Feature Fill, Parametric, and Reliability

Cu films were directly deposited on Ru to check the feasibility of this process for Cu back-end-of-the-line integration beyond 32-nm technology nodes. Feature-fill enhancement was observed from the direct electroplating process as compared to the conventional one with the Cu electroplating performed on a PVD Cu seeding layer. Reasonable parametric yields were demonstrated for the direct electroplating process. The electromigration (EM) resistance of the directly plated Cu lines was degraded relative to that observed on the conventionally plated Cu lines. The observed EM resistance degradation is attributed to a weak interface between Ru/Cu, which can be caused by impurities from the electroplating process.