Balasubramanian S. Haran

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Extremely thin SOI (ETSOI) technology: Past, present, and future

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (L_G) of 20nm and BOX thickness (T_BOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (I_eff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (I_off) of 100nA/μm and V_dd of 0.9V. Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond. Very low A_Vt (1.3mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

We report FDSOI devices with a 20nm gate length (L_G) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V_dd of 0.75V, competitive effective current (I_eff) reaches 550/340 μA/μm for NFET, at I_off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V_dd of 0.75V, PFET I_eff reaches 495/260 μA/μm, at I_off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.

An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond

This paper addresses a critical CMOS challenge of increasing parasitic resistance by introducing electroplated rhodium (Rh) as an alternative middle-of-line (MOL) metallurgy to replace the conventional CVD tungsten (W) processes for lower contact resistance and better extendibility to 32 nm technology and beyond. Electroplating of Rh is shown to have similar to Cu superconformal filling capability, allowing us to successfully fill high aspect ratio vias (40 nm times 240 nm). Plating of 300 mm wafers with 60 nm times 290 nm vias was demonstrated using CVD or ALD ruthenium (Ru) as the seed layer. An annealing process was developed to obtain a thin Rh film resistivity of 6.5 muOmega-cm, which is 1.5 to 3X lower than the resistivity of CVD W films. Since Rh is stable in Si environment, when compared to a fast diffusing Cu, a very thin Ti/Ru layer can be implemented. Therefore we propose to use PVD Ti/ALD Ru/electroplated Rh as the alternative MOL metallurgy. With this simple liner/seed/fill stack, the overall MOL resistance is calculated to be 2x lower than the overall MOL resistance of the conventional W stacks, and slightly lower than Cu fill stacks. In addition, the ability to use a thinner liner layer than that used for Cu-base fill process, provides a greater potential for extendibility of Rh fill into future CMOS MOL generations.

Tungsten and cobalt metallization: A material study for MOL local interconnects

Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.

Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.