Sooryong Lee

OPC in memory-device patterns using boundary layer model for 3-dimensional mask topographic effect

Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.

A simplified reaction-diffusion system of chemically amplified resist process modeling for OPC

As semiconductor manufacturing moves to 32nm and 22nm technology nodes with 193nm water immersion lithography, the demand for more accurate OPC modeling is unprecedented to accommodate the diminishing process margin. Among all the challenges, modeling the process of Chemically Amplified Resist (CAR) is a difficult and critical one to overcome. The difficulty lies in the fact that it is an extremely complex physical and chemical process. Although there are well-studied CAR process models, those are usually developed for TCAD rigorous lithography simulators, making them unsuitable for OPC simulation tasks in view of their full-chip capability at an acceptable turn-around time. In our recent endeavors, a simplified reaction-diffusion model capable of full-chip simulation was investigated for simulating the Post-Exposure-Bake (PEB) step in a CAR process. This model uses aerial image intensity and background base concentration as inputs along with a small number of parameters to account for the diffusion and quenching of acid and base in the resist film. It is appropriate for OPC models with regards to speed, accuracy and experimental tuning. Based on wafer measurement data, the parameters can be regressed to optimize model prediction accuracy. This method has been tested to model numerous CAR processes with wafer measurement data sets. Model residual of 1nm RMS and superior resist edge contour predictions have been observed. Analysis has shown that the so-obtained resist models are separable from the effects of optical system, i.e., the calibrated resist model with one illumination condition can be carried to a process with different illumination conditions. It is shown that the simplified CAR system has great potential of being applicable to full-chip OPC simulation.

OPC to account for thick mask effect using simplified boundary layer model

We present simplified symmetric boundary layer model (BLM) for Optical Proximity Correction (OPC) in order to account for thick (or 3D or topographic) mask effect. In this approach, near-field mask image which is quite different from original mask pattern due to mask topography is approximated as the original pattern and boundary layer around it. In this work, the boundary layer is determined as such that residual critical dimension (CD) error between measured CD and modeled CD from the BLM is minimized for various types of features. In case of sub-50 nm memory patterning, this BLM shows sufficient accuracy that root mean square of the residual CD is as small as 4.3 nm. Also, OPC speed with BLM is reasonably fast as the OPC time with BLM increases as only around twice as the conventional OPC time without BLM, which is acceptable in practice.

Fine calibration of physical resist models: the importance of Jones pupil, laser bandwidth, mask error and CD metrology for accurate modeling at advanced lithographic nodes

In this paper, we discuss the accuracy of resist model calibration under various aspects. The study is done based on an extensive OPC dataset including hundreds of CD values obtained with immersion lithography for the sub-30 nm node. We address imaging aspects such as the role of Jones matrices, laser bandwidth and mask bias. Besides we focus on the investigation on metrology effects arising from SEM charging and uncertainty between SEM image and feature topography. For theses individual contributions we perform a series of resist model calibrations to determine their importance in terms of relative RMSE (Root Mean Square Error) and it is found that for the sub-30 nm node they all are not negligible for accurate resist model calibration.

Improvement in process window aware OPC

In this paper, we present some important improvements on our process window aware OPC (PWA-OPC). First, a CDbased process window checking is developed to find all pinching and bridging errors; Secondly, a rank ordering method is constructed to do process window correction; Finally, PWA-OPC can be applied to selected areas with different specifications for different feature types. In addition, the improved PWA-OPC recipe is constructed as sequence of independent modules, so it is easy for users to modify its algorithm and build original IPs.

Robust approach to determine the optimized illumination condition using process window analysis

Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope (NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition. NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window (PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted. Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of calculations, the fast calculation speed can be obtained by using the distributed process.

Improvement on post-OPC verification efficiency for contact/via coverage check by final CD biasing of metal lines and considering their location on the metal layout

As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by k1 factor. To guarantee the imaging fidelity, resolution enhancement technologies (RET) such as off-axis illumination (OAI), different types of phase shift masks and OPC technique have been developed. In case of model-based OPC, to cross-confirm the contour image versus target layout, post-OPC verification solutions continuously keep developed - contour generation method and matching it to target structure, method for filtering and sorting the patterns to eliminate false errors and duplicate patterns. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process - to save not only reviewing time and engineer resource, but also whole wafer process time and so on. In general case of post-OPC verification for metal-contact/via coverage (CC) check, verification solution outputs huge of errors due to borderless design, so it is too difficult to review and correct all points of them. It should make OPC engineer to miss the real defect, and may it cause the delay time to market, at least. In this paper, we studied method for increasing efficiency of post-OPC verification, especially for the case of CC check. For metal layers, final CD after etch process shows various CD bias, which depends on distance with neighbor patterns, so it is more reasonable that consider final metal shape to confirm the contact/via coverage. Through the optimization of biasing rule for different pitches and shapes of metal lines, we could get more accurate and efficient verification results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using simple biasing rule to metal layout instead of etch model application is presented.

AF Fixer : New incremental OPC method for optimizing Assist Feature

Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AFs print more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present, mask manufacturers must downsize AFs below 30nm to solve this problem. This is challenging and increases mask cost. We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in terms of DOF after OPC. We have devised an effective algorithm that removes printing AFs. It can not only search for the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF printing problems economically and accurately.

Mask process effect aware OPC modeling

Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict the entire lithography process correctly even using advanced optical and resist models. In order to compensate for the mask proximity effect within OPC a special model is required along with changes to the OPC flow. This article presents a method for producing such a model and OPC flow and shows the difference in results when they are used.

Stray-light implementation in optical proximity correction (OPC)

It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and presents how to solve the problems.