Sungsoo Suh

Fast and accurate 3D mask model for full-chip OPC and verification

A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and the thick-mask model based on Hopkins treatment of oblique incidence.

The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate

This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation) control become more important to meet the performance goal for high speed in DRAM. The main factors which influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density difference between spider mask and real gate mask, the skew difference occurs between them. We tested the effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10 mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm). This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce this skew difference between spider mask and real mask, we applied open field mask correction term and long range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up to 67%.

Enhancing fullchip ILT mask synthesis capability for IC manufacturability

It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh[1][2] thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including: DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask. Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors responsible for their differences include composition of the cost function that is minimized, constraints applied during optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.

OPC in memory-device patterns using boundary layer model for 3-dimensional mask topographic effect

Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.

Hotspot fixing using ILT

For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the layout. The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.

OPC to account for thick mask effect using simplified boundary layer model

We present simplified symmetric boundary layer model (BLM) for Optical Proximity Correction (OPC) in order to account for thick (or 3D or topographic) mask effect. In this approach, near-field mask image which is quite different from original mask pattern due to mask topography is approximated as the original pattern and boundary layer around it. In this work, the boundary layer is determined as such that residual critical dimension (CD) error between measured CD and modeled CD from the BLM is minimized for various types of features. In case of sub-50 nm memory patterning, this BLM shows sufficient accuracy that root mean square of the residual CD is as small as 4.3 nm. Also, OPC speed with BLM is reasonably fast as the OPC time with BLM increases as only around twice as the conventional OPC time without BLM, which is acceptable in practice.

Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT

Design for Manufacturing (DFM) is being widely accepted as one of keywords in cutting edge lithography and OPC technologies. Although DFM seems to stem from designers intensions to consider manufacturability and ultimately improve the yield, it must be well understood first by lithographers who have the responsibility of reliable printing for a given design on a wafer. Current lithographers understanding of DFM can be thought of as a process worthy design, and the requirements set forth from this understanding needs to be well defined to a designer and fed forward as a necessary condition for a robust design. Provided that these rules are followed, a robust and process worthy design can be achieved as a result of such win-win feed-forward strategy. In this paper, we discuss a method on how to fully analyze a given design and determine whether it is process worthy, in other words DFM-worthy or not. Mask Error Enhancement Factor (MEEF), Through Focus MEEF (TF-MEEF) and Mean-To-Target (MTT) values for an initial tentative design provide good metrics to obtain a robust and process worthy design. Two remedies can be chosen as DFM solutions according to the aforementioned analysis results: modify the original design or manipulate the layout within a design tolerance during OPC. We will discuss on how to visualize the analyzed results for the robust and process worthy OPC with some relevant examples. In our discussions, however, we assumed that the robust model be being used for each design verification, and such a model derived with more physical parameters that correlates better to real exposure behavior. The DFM can be viewed as flattening the TF-MEEF across the design.

Model-based assist feature insertion for sub-40nm memory device

Many issues need to be resolved for a production-worthy model based assist feature insertion flow for single and double exposure patterning process to extend low k1 process at 193 nm immersion technology. Model based assist feature insertion is not trivial to implement either for single and double exposure patterning compared to rule based methods. As shown in Fig. 1, pixel based mask inversion technology in itself has difficulties in mask writing and inspection although it presents as one of key technology to extend single exposure for contact layer. Thus far, inversion technology is tried as a cooptimization of target mask to simultaneously generate optimized main and sub-resolution assists features for a desired process window. Alternatively, its technology can also be used to optimize for a target feature after an assist feature types are inserted in order to simplify the mask complexity. Simplification of inversion mask is one of major issue with applying inversion technology to device development even if a smaller mask feature can be fabricated since the mask writing time is also a major factor. As shown in Figure 2, mask writing time may be a limiting factor in determining whether or not an inversion solution is viable. It can be reasoned that increased number of shot counts relates to increase in margin for inversion methodology. On the other hand, there is a limit on how complex a mask can be in order to be production worthy. There is also source and mask co-optimization which influences the final mask patterns and assist feature sizes and positions for a given target. In this study, we will discuss assist feature insertion methods for sub 40-nm technology.

Merged Contact OPC using Pattern Type Specific Modeling and Correction

Traditional approach to model based optical proximity correction method is to collect a set of 1-D and 2-D test pattern data, calibrate a scalar or vector model at constant or variable threshold and modify the physical layout to obtain the desired layout. Optical proximity corrected layout is obtained by minimizing the error between the target and the printed image iteratively using a calibrated single model to generate a simulated print image of mask pattern of variety of field polarity. A similar approach can be extended to incorporate the final silicon image using a lumped model or tandem photo-resist development and etch process models. Recently, some have begun to incorporate differing models at specific regions of the layout. The basic underlying assumption of a model-based OPC requires one to generate a simulated contour that provides close approximation of wafer image using a calibrated model. During iterative OPC procedure, not all of the regions of OPC polygons are simulated. That is, sparse sampling of each polygon is performed to reduce the number of error calculations required and such calculation points are referred to as an evaluation site. A careful selection of sampling site must be performed to capture optical proximity effect and obtain the desired OPC. In this paper, utilization of multiples models to generate contour to accurately define the 2D pattern locally, and implementation of its models throughout the layout is presented in order to improve accuracy of variety of contact pattern types present in a layout. Hence, the basic concept is to apply differing models at localized region and achieve greater OPC accuracy than a single calibrated model. In particular, a target layout may contain a contact and bar-type structures for the purpose of device fabrication process step simplifications. Essentially, two different pattern types need to be OPCed, and in order to perform model based OPC on such a layout, a model for each contact type is generated separately using a best-fit adaptive search method of optical illumination conditions, aerial image diffusion parameter and double Gaussian mask loading terms as a main regression parameters. As it terms out, it is difficult to generate a single model that calibrates to both the contact and bar-type structures and a distinct shift in empirically calibrated threshold levels exists, and a preferred method is to generate models suited for contact and bar-type structures separately in order to improve the model and OPC accuracy. However, each model type needs to be applied at specific locations of a pattern, and a proper OPC recipe for handling biasing of each pattern type is needed as well as correction scheme suitable for each pattern type is required. In this paper, we describe an OPC methodology for merged direct contact layout using a proposed pattern specific modeling and correction technique, and the experimental results indicate that this methodology provides ADI 3s target skew value of 14 nm and ACI 3σ target skew value of 17 nm on a 60 nm half pitch node.

Robust approach to determine the optimized illumination condition using process window analysis

Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope (NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition. NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window (PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted. Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of calculations, the fast calculation speed can be obtained by using the distributed process.