Sophie Puget

FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications

A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time. A similar value of 10 ms at 85degC is obtained like for impact ionization (II) optimised devices.

Quantum effects influence on thin silicon film capacitor-less DRAM performance

As DRAM integration follows CMOS interest for thin silicon films, we analyze the impact of quantum effects on capacitor-less DRAM based on floating-body effect. Quantum effects significantly reduce the memory effect when silicon film reaches 10nm but their major impact is for thin and undoped silicon film

Independent Double Gate - potential for non-volatile memories

The authors proposed an analysis of the IDG device as a potential non volatile memory cell. IDG allows the most extended electrical combinations compared to the SQeRAM and consequently a large range of use. The two gates of the transistor are dynamically and separately addressable.

On the potentiality of planar independent double gate for capacitorless eDRAM

Thin film devices are potential candidates for the 32 nm technology node and beyond. In this perspective, thin film architecture as embedded capacitorless eDRAM remains to be assessed. Planar Independent Double Gate architecture is considered here. The analysis of technological parameters and their scaling are evaluated on memory effect. Optimal gate stack for IDG appears to be metal /poly P+ combination for this architecture.

Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET

In this paper, we present the investigation of narrow-width effects (NWEs) on partially depleted (PD) silicon-on-insulator (SOI) with different gate shape topologies. Based on dc/ac measurements and TCAD simulations, it shows detailed clarifications of body-tied-induced NWEs. The overall study demonstrates relationship between gate shape topologies, body-tied shape, and electrical width of the transistor. Provided physical-based analytical models are able to capture peak GM and CGG as function of gate length, transistor width, physical gate-overlap width, and number of body tied. This results in improving the overall model accuracy of body contact and floating-body PD SOI MOSFETs.

Modeling the Independent Double Gate Transistor in Accumulation Regime for 1TDRAM Application

This paper details the modeling of a one-transistor dynamic random-access memory (1TDRAM) based on an independent double-gate device. A pseudo-2-D compact model of memory operations and dynamic behavior of data retention is proposed. The physical mechanisms involved are calculated through the accumulated charge in the body modulated by quantum effects related to thin silicon films. The resulting currents from programming operations are detailed. We consider current leakages, generation/recombination, and band-to-band tunneling parasitic effects for data retention.