Sou-Chi Chang

Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

The possibility of using spin waves for information transmission and processing has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits with less physical resources and low power consumption. Previous proposals on spin wave logic circuits have suggested the idea of utilizing the magneto-electric effect for spin wave amplification and amplitude- or phase-dependent switching of magneto-electric cells. Here, we propose a comprehensive scheme for building a clocked non-volatile spin wave device by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, magneto-electric spin wave repeaters that operate in three different regimes - spin wave transmitter, non-volatile memory and spin wave detector, and a novel clocking scheme that ensures sequential transmission of information and non-reciprocity. The proposed device satisfies the five essential requirements for logic application: nonlinearity, amplification, concatenability, feedback prevention, and complete set of Boolean operations.

Design and Analysis of Copper and Aluminum Interconnects for All-Spin Logic

In this paper, a conventional spin-valve configuration combined with spin-torque-driven switching is used as an energy efficient interconnect structure for all-spin logic. Both Cu and Al interconnect materials are analyzed based on physical models for spin injection, spin transport, and magnetization dynamics. The results indicate proposed metallic interconnects dissipate less energy as compared with all-spin logic interconnects based on the nonlocal spin-valve configuration. Compared with a similar spin interconnect with an Si channel, the spin currents and injection efficiencies are predicted to be higher when a metal like Cu or Al is used due to no Schottky barrier at the interface. Because of the longer spin relaxation length (SRL) in Al as compared with Cu, the delay and energy dissipation are lower when Al is used especially at longer lengths where signal loss becomes important. While metallic spin interconnects are faster and more energy efficient in short lengths because of their smaller resistances and higher spin injection efficiencies, they are outperformed by spin interconnects with Si channels at long lengths because the SRLs in Si can be as long as many micrometers, whereas in metals they are limited to a few hundred nanometers.

Design and Analysis of Si Interconnects for All-Spin Logic

An Si spin interconnect for all-spin logic (ASL) is analyzed by a comprehensive physical model, including spin injection, spin transport, and stochastic magnetization dynamics. It is shown that the spin current density and spin polarization of the current can be improved by changing material properties, interface conditions, and structure dimensions. Furthermore, with the help of an electric field, spin information can preserve and propagate between magnets in a highly doped micrometer-scale Si channel. Different from metallic ASL, instead of the short spin relaxation length, the main constraint of an Si spin interconnect is the high bias voltage required to minimize the energy-delay product (EDP). The minimum EDP and corresponding bias voltage can be reduced significantly by downscaling the nanomagnet. This improvement in the magnetic response allows Si to provide a compatible low-power interconnect technology to metallic ASL.

Temperature-Oriented Mobility Measurement and Simulation to Assess Surface Roughness in Ultrathin-Gate-Oxide (

On a 1.27-nm gate-oxide nMOSFET, we make a comprehensive study of SiO₂/Si interface roughness by combining temperature-dependent electron mobility measurement, sophisticated mobility simulation, and high-resolution transmission electron microscopy (TEM) measurement. Mobility measurement and simulation adequately extract the correlation length λ and roughness rms height Δ of the sample, taking into account the Coulomb-drag-limited mobilities in the literature. The TEM measurement yields the apparent correlation length λ<i>m</i> and roughness rms height Δ<i>m</i>. It is found that the following hold: 1) λ ≈ λ<i>m</i> for both the Gaussian and exponential models, validating the temperature-oriented extraction process; 2) the extracted Δ (~1.3 Å for the Gaussian model and 1.0 Å for the exponential one) is close to that (~1.2 Å) of Δ<i>m</i>, all far less than the conventional values (~3 Å) in thick-gate-oxide case; and 3) the TEM 2-D projection correction coefficient Δ<i>m</i>/Δ is approximately 1.0, which cannot be elucidated with the current thick-gate-oxide-based knowledge.

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A systematic study on the feasibility of an error-free switching of two nanomagnets coupled via their dipolar fields by applying a spin current to one of them is presented. It is demonstrated that the dynamic nature of dipolar interaction between the nanomagnets may cause the magnetization of the second magnet to precess back to its original state despite having crossed the free-axis equatorial plane during the transient phase. This non-reversal is very different than the purely successful or unsuccessful switchings noted in other reversal analyses presented in the literature and, in this paper, is referred to as a dipolar switching glitch. The dynamic dipolar coupling between nanomagnets creates temporary titled precessional trajectories pushing the magnetization of the nanomagnet into high-energy states. Relaxation from these high-energy positions leads to fast, but quasi-random switching behavior. The maximum separation between the magnets for perfect coupling has been quantified as a function of the magnet planar dimensions. It is also shown that the simpler models that do not consider the mutual coupling between the two magnets underestimate the maximum allowed separation between the two magnets and, as such, are too conservative.

1 nm) nMOSFETs and Its TEM Evidence

Scaling limits on all-spin logic (ASL) are theoretically studied using the spin circuit theory and the stochastic Landau-Lifshitz-Gilbert equation under the macrospin approximation. It is found that as ASL circuits are scaled, the device delay significantly increases due to a stronger dipole coupling between the input and the output magnets. The effect of the dipole interaction can be mitigated by increasing the input current and by using smaller magnets with stronger material anisotropy and weaker saturation magnetization. Furthermore, the presence of the leakage current modifies the device delay. Finally, both delay and energy of ASL dramatically increase as the shunt path is shortened. Possible solutions to eliminate the leakage current and the shunt path are discussed.

A Model Study of an Error-Free Magnetization Reversal Through Dipolar Coupling in a Two-Magnet System

In this paper, a theoretical approach, comprising the non-equilibrium Greens function method for electronic transport and Landau-Khalatnikov equation for electric polarization dynamics, is presented to describe polarization-dependent tunneling electroresistance (TER) in ferroelectric tunnel junctions. Using appropriate contact, interface, and ferroelectric parameters, measured current-voltage characteristic curves in both inorganic (Co/BaTiO

Scaling Limits on All-Spin Logic

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Theoretical Approach to Electroresistance in Ferroelectric Tunnel Junctions

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Clocked Domain Wall Logic Using Magnetoelectric Effects

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