Sriram Muthukumar

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Near-threshold computing brings the promise of an order of magnitude improvement in energy efficiency over the current generation of microprocessors [1]. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all single-threaded or performance-constrained applications. Enabling the processor to operate over a wide voltage range helps to achieve best possible energy efficiency while satisfying varying performance demands of the applications. This paper describes an IA-32 processor fabricated in 32nm CMOS technology [2], demonstrating a reliable ultra-low voltage operation and energy efficient performance across the wide voltage range from 280mV to 1.2V.

Integrated on-chip inductors using magnetic material (invited)

On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μ H / mm 2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability ( > 250 ° C ) , high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz , but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω , and quality factors up to 8 at frequencies as low as 40 MHz.

Fabrication and electrical characterization of 3D vertical interconnects

3D die-stacking (Tanida et al, 2003; Hara et al, 2005) and wafer-stacking (Morrow et al, 2004) integration have recently been demonstrated using copper (Cu) interconnections and through silicon via technology. In 3D die-stacking approach, the Cu vertical interconnections are fabricated on the front-side of the silicon wafer along with the active circuitry followed by wafer thinning and die-stacking. The limitation of this approach is the impact to active circuitry from vertical interconnects processing. With the 3D wafer stacking approach, the wafers are bonded with the prefabricated active circuitry face-to-face prior to wafer thinning and Cu interconnects fabrication and inherently limit stack die configuration to matched die sizes. This approach has inherent benefits and limitations depend to a large extent on the targeted applications. In this paper, we present an alternate 3D die-stacking approach which involves wafer thinning prior to Cu interconnect fabrication in a silicon wafer consisting of pre-fabricated active circuitry. This approach allows for mixed die size and technology node integration in multi-chip packages while maximizing known good die yields. In this approach the electrical connection to the active circuitry is made through the Cu plated through-silicon via to large arrays of tungsten (W) contacts at the bulk silicon interface. The challenges in through-silicon via processing using this 3D die-stacking approach will be discussed. Backside processing impact to pre-fabricated transistors and fundamental RC performance of the through silicon via landing on contact will be presented

Design and Fabrication of 3D Microprocessors

Stacking multiple device strata can improve system performance of a microprocessor (μP) by reducing interconnect length. This enables latency improvement, power reduction, and improved memory bandwidth. In this paper we review some of our recent design analysis and process results which quantitatively show the benefits of stacking applied to μPs. We report on two applications for stacking which take advantage of reduced wire length- “logic+logic” stacking and “logic+memory” stacking. In addition to optimizing minimum wire length, we considered carefully the thermal ramifications of the new designs. For the logic+memory application, we considered the case of reducing off-die wiring by stacking a DRAM cache (32 to 64MB) onto a high performance μP. Simulations showed 3x reduced off-die bandwidth, Cycles Per Memory Access (CPMA) reduction of 13%, and a 66% average bus power reduction. For logic+logic applications, we considered a high performance μP where the unit blocks were repartitioned into two strata. For this case, simulations showed that stacking can simultaneously reduce power by 15% while increasing performance by 15% with a minor 14° C increase in peak temperature compared to the planar design. Using voltage scaling, this translates to 34% power reduction and 8% performance improvement with no temperature increase. We found that these results can be further improved by a secondary splitting of the individual blocks. As an example, we split a 32KB first level data cache resulting in 25% power reduction, 10% latency reduction, and 20% area reduction. We also discuss the fabrication of stacked structures with two complimentary process flows. In one case, we developed a 300mm wafer stacking process using Cu-Cu bonding, wafer thinning, and through-silicon vias (TSVs). This technology provides reliable bonding with non-detectable bonding-interface resistance and inter-strata via pitch below 8μm. We investigated the impact of this wafer stacking process to the transistor and interconnect layers built using a 65nm strained-Si/Cu-Low-K process technology and found no impact to either discrete N- and P-MOS devices or to thin 4Mb SRAMs. We verified fully functional SRAMs on thinned wafers with thicknesses down to 5μm. Although wafer stacking leads itself well to tight-pitch same-die-size stacking, die stacking enables integration of different size dies and includes opportunity to improve yield by stacking known good dies. We demonstrated a die stack process flow with 75μm thinned die, TSV, and inter-strata via pitch below 100μm. We also found negligible impact to transistors using this process flow. Multiple stacks of up to seven 75μm thin dies with TSVs were fabricated and tested. Prospects for high volume integration of 3D into μPs are discussed.

High-density compliant die-package interconnects

Reduction in inter-level dielectric (ILD) constant has been accompanied by a reduction in ILD adhesive and cohesive strength thus increasing potential for under bump (flip-chip) ILD cracking during packaging and reliability testing. Two primary mechanisms were determined to cause this failure: (1) stress on the ILD created due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the package substrate; and (2) the die-to-package interconnection, i.e. the bump, transmits the CTE-induced mismatch stresses directly to the ILD (Chandran et al., 2004). Compliant die-package interconnects (Zhu et al., 2004) substituted for conventional C4 flip-chip interconnections promises to offer reduction in package induced stresses onto the silicon die consisting of low-k ILD layers. The reduction of stresses achieved with these compliant interconnects is by decoupling the die and the package substrate such that either entity is able to deform without constraining the other. Extensive thermomechanical simulation using various modeling approaches predicts an ILD stress reduction offered by compliant interconnects to be between 17-57% relative to conventional C4 flip-chip bump. A prototype compliant interconnect structure was fabricated on a low-k ILD silicon test-chip with 180mum C4 pitch and packaged onto an organic substrate with Pb-free solder. Assembly end-of-line (EOL) data was collected to assess the ILD stress reduction, warpage analysis, Imax and electromigration performance of the compliant interconnects. The focus of this paper is a comparison of the performance of compliant die-package interconnects as a substitute for conventional C4 flip-chip bump technologies in low-k ILD architectures

Reliable Design of Electroplated Copper Through Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2 , interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.Copyright

Coreless substrate technology investigation for ultra-thin CPU BGA packaging

Coreless packaging is an attractive option to meet the low z-height requirements typically demanded in low-profile mobile devices. In order to deliver high quality, fully functional assembled coreless packages several aspects of this technology need to be studied to understand the benefits and the drawbacks. Towards realizing this goal, a prototype coreless BGA package for an existing product was designed, fabricated, and characterized for power delivery and IO signal integrity. A comparative study of performance was performed on a 45nm CPU in a coreless BGA package, and compared to the same 45nm CPU in the standard cored BGA. This paper reviews the design strategies implemented and characterization data collected to achieve matched electrical performance with the existing cored package. The paper first makes comparisons between cored and coreless designs and then presents the detailed physical design concepts. Next the paper focuses on electrical performance analysis including both IO performance and power delivery analysis, and then reviews the validation data collected. The results of this study show that the IO performance is comparable between the cored and coreless packages for both microstrip and the stripline routing for both DDR3 and PCI Express Gen 2. Additionally, the power delivery study shows that the expected benefit from the removal of PTHs is compromised in this prototype design due to the removal of die side capacitors and the reduction in the total number of land side capacitors. This made the coreless DC loadline virtually unchanged when compared to the cored package.

3-D integrated inductor on silicon backend using compliant interconnect process for 10GHz low jitter VCO application

This paper presents a 3-D integrated coil inductor fabricated on silicon backend for 10GHz LC type (L for inductance, C for capacitance) voltage-controlled oscillator (VCO) for low jitter VCO applications , with improved quality factor (Q) of on-chip inductors. The 3-D inductor is formed using a compliant interconnect processing method used for flip chip technologies (Muthukumar, 2006). The compliant die-package interconnects are designed to have a very small inductance (100~200pH) to minimize the insertion loss for high-frequency signals (Braunisch, 2004). Using this compliant interconnect processing method a 3-D high Q coil inductor with inductance of 0.8~1.2nH for low jitter LC type VCO applications at 10GHz can be fabricated. At high frequencies, the higher the Q of the inductor, the lower is the jitter/phase noise of the LC VCO. A 2-D integrated inductor in a package substrate having Q higher than a 2-D on-chip inductor can also be used for 10GHz VCO application. However, the additional routing trace inductance resulting from the integrated inductor in package substrate may limit the implementation of LC-tank part of the VCO compared to a high Q 3-D coil inductor located on silicon backend. This paper presents the design of a 3-D coil for the 10GHz low jitter VCO application, the simulated performance of the 3-D coil and 2-D integrated inductors in package substrate using Ansoft HFSS, and a method to fabricate and integrate the 3-D coil on the silicon backend layers

Characterization of Novolac Based Photoresists to Fabricate 3D Polymer Dome Features

Wafer level, 3D, free standing structures (e.g., domes or hemi-cylinders) can be fabricated using polymer dome features as sacrificial templates for MEMS and interconnect applications. Understanding the kinetics of dome formation and the material properties are essential for a robust and manufacturable process of controlling the size and shape of the photoresist features. In this paper, temporal and thermal characteristics of Novolac based photoresists are presented as a function of solid loading and solvent type using analytical techniques such as Thermogravimetric Analysis (TGA), Fourier Transform Infrared (FTIR) spectroscopy, hot stage microscopy, and Gas Chromatography/ Mass Spectrometry (GC/MS). The solid loading influences the thickness and processing ability of the resist. The solvent evaporation rate controls the final size and shape of the 3D polymer dome features. Solvent is the primary material lost during the dome formation and the onset of deformation is dependent on temperature and ramp rate.Copyright

A Four-Channel Electrical Impedance Spectroscopy Module for Cortisol Biosensing in Sweat-Based Wearable Applications:

A four-channel electrochemical impedance spectroscopy (EIS) analyzer module has been demonstrated on flexible chemi-impedance sensors fabricated with gold electrodes for wearable applications. The module can perform time division multiplexed (TDM) impedance measurements on four sensors at 1 kHz. In this work, we characterize the system for the detection of cortisol in an ultralow volume (1–3 µL) of perspired human sweat, sensor performance, and effects during continuous cortisol dosing and with pH and temperature variations expected on the surface of the skin that would be representative of use conditions as seen by a wearable device. Detection of cortisol was shown for concentrations of 1 pg/mL to 200 ng/mL in both synthetic and perspired human sweat, and output response reported as a change in impedance with varying cortisol concentrations. Continuous dose testing was performed to demonstrate the stability of the sensors over prolonged periods of operation for cortisol concentrations within the physiologically relevant range of 10–200 ng/mL reported in human sweat. Temperature and pH effects testing was performed for pH range 4–8 and in a temperature chamber for the clinical range reported on the surface of human skin: 25–40 °C. The cortisol sensor demonstrated stability of operation with 7.58% variability under these conditions.