Stefan Gogaert

Low-voltage analog CMOS filter design

Design techniques for low-voltage analog filters in CMOS technologies are discussed. The use of operational transconductance amplifier (OTA)-C implementation techniques toward low power supply voltages (3 V and below) requires special source degeneration and input signal folding techniques. Design techniques to achieve full CMOS continuous-time filters with low distortion (total harmonic distortion < -50 dB) and low power supply voltages (3 V) are discussed. The use of switched-capacitor techniques at extremely low voltages (1.5 V) requires extra care for the switches in the circuit. Special design techniques, such as voltage multipliers for the clock drivers and single transistor switches, are analyzed to achieve the low power supply specifications.<<ETX>>

A Low-power portable telemetry system for eight channel EMG measurements

A telemetry system which can measure u p to eight different EMG signals at the same time is presented. The system is full portable, c ontaining a bidirectional telemetry link with a personal computer. The whole system has been optimized to achieve a low-power measuring system, without losing any signal information up to 250 Hz. All settings of the system c an be set and controlled by the personal computer.

622 Mbit/s board-to-board link in 0.5 /spl mu/m CMOS technology

High speed digital processing chips demand also high speed interconnections. On-board communication with a limited distance have already been realised. However in this paper an inter board communication over a relative long distance is presented. To minimise signal reflections in this kind of communication networks a special termination circuit has been developed. This impedance termination can be tuned to match the characteristic impedance of the transmission wire. Using this termination circuit a driver and receiver are designed. Transmission rates up to 800 Mbit/s have been measured. The two boards are connected to each other with a twin ax shielded wire plugged in the backplane connector of the two PCBs. To allow integration with the digital processing chips a standard CMOS process is used to realise the driver and receiver chips.

A skew tolerant CMOS level-based ATM data-recovery system without PLL topology

In high-speed communication systems with multiple inputs from different origins, all data have to be retimed to the clock of the DSP. This paper describes a data-recovery system which allows a 25% tolerance on the absolute position of the edge. The intelligent sample selector with memory-function retrieves the correct data from the multisampled input, even under the circumstances of wander, clock- and data-jitter and propagation phase-shift. The used approach does not require a PLL nor a DLL, since the straightforward mechanism results in the capture of the transmitted data with only the use of the central clock of the DSP. The retiming is done already at the first level-change and further at each following level-change. The good results are proven with measurements on a realisation with standard cells in a standard 0.7 /spl mu/m CMOS technology.

Full CMOS continuous time filters for GSM applications

This paper describes full cmoscontinuous time filter design techniques which can meet the specifications commonly set for gsmapplications. First several cmosfilter design techniques are overviewed. The ota-ctechnique is discussed to some more detail. To overcome the main drawback of the lower total harmonic distortion in ota-ctechniques very linear operational transconductance amplifiers (ota)are required. Such an ota,together with the applied linearisation techniques is discussed. To fulfil high accuracy in cut- off frequencies of the filter an active tuning system is necessary. A new on- chip tuning system is presented. The paper concludes with a practical design example for the gsmsystem. Therein the different ota-ctechniques discussed are illustrated.Résuméľarticle décrit la réalisation de filtres analogiques àtemps continu plutôt qu’àdonnées échantillonnées,en insistant sur la technologie ota-cbasée sur des condensateurs et des amplificateurs opérationnels du type transconductance. Cette technologie est comparée àcelles des capacités commutées et des filtres actifs rc.Elle utilise un transducteur linéaire de tension en courant. Une linéaritéélevée permet de maintenir une faible distorsion harmonique. Un accord automatique de fréquence sur la puce est nécessaire pour obtenir une grande précision des fréquences de coupure. Un exemple concret est un passe- bas de Legendre du 4eordre.

A 1 Gbit/s full-duplex CMOS driver/receiver for twisted-pair data-communication

In this work, the realisation of a chip in a 0.5 /spl mu/m CMOS process capable of full-duplex communication on a twisted pair cable at a speed of 1 Gbit/s is presented. It includes an on-chip impedance matching circuit to match the circuit to the cable impedance. The chip runs at 3.3 V power supply and consumes about 57 mA. Measurements are done with a 2.2 meter twin-ax-shielded pair between two of these chips.