Jan Crols

Low-IF topologies for high-performance analog front ends of fully integrated receivers

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology

An analog receiver front end chip realized in a 0.7 /spl mu/m CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3/spl deg/ in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products.

Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages

The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-/spl mu/m CMOS process with V/sub T/=/spl plusmn/0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV/sub ptp/ and a powerdrain of only 110 /spl mu/W. >

CMOS wireless transceiver design

Symbols, Conventions, Notations and Abbreviations. Preface. 1. Wireless Communications. 2. Transmitters and Receivers. 3. Transceivers in the Frequency Domain. 4. Performance of Transceivers. 5. High-Level Synthesis. 6. Building Blocks for CMOS Transceivers. 7. Realizing A CMOS Transceiver. 8. General Conclusions. Appendices. A-Process Information. Bibliography. Index.

A 1.5 GHz highly linear CMOS downconversion mixer

A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 /spl mu/m CMOS process. It takes up 1 mm/sup 2/ of total chip area and its power consumption is 1.3 mW from a single 5 V power supply. >

An analog integrated polyphase filter for a high performance low-IF receiver

An analog integrated asymmetric polyphase filter is a key building block for the development of a high performance fully integrated low-IF receiver. The asymmetric polyphase filter makes it possible to suppress the mirror signal not at HF, but after quadrature demodulation at a low IF. The most important parameters for the polyphase filter are a high dynamic range and a good mirror signal suppression. This paper reports on the realisation in a 1.2 /spl mu/m CMOS process of a 5th order Butterworth polyphase filter with a bandwidth of 220 kHz centered around 250 kHz. Its measured mirror signal suppression is 64 dB. The active-RC implementation renders a 94.2 dB dynamic range at the input.

A single-chip CMOS transceiver for DCS-1800 wireless communications

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.

A CMOS 18 THz/spl Omega/ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 /spl mu/m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is 60 mA which allows a 155 Mb/s optical data-rate. The receiver is a three-stage transimpedance amplifier followed by a signal converter which provides digital output signal levels. The three-stage configuration makes possible the realization of a high transimpedance (150 k/spl Omega/), necessary to obtain a high sensitivity, combined with a high bandwidth. The achieved optical data-rate is 240 Mb/s for 1 /spl mu/A input modulation currents. This results in a transimpedance bandwidth of 18 THz/spl Omega/, which is one order of magnitude higher than recently published circuits. The speed performance of the total link is limited by the optical time-constant of the LED, leading to a 155 Mb/s optical link, designed for use in four-fiber interboard connections in 622 Mb/s B-ISDN systems. >

An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz

An analytical model for planar inductors in air or on lowly doped substrates has been introduced. The model parameters have been fitted by means of electromagnetic simulation and its validity has been verified with measurement results. In this paper it has also been shown how this analytical model can be used to gain a better insight in technology, layout and design trade-offs.

A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communications

A low-power, broadband LNA has been integrated in a standard 0.5 /spl mu/m CMOS process. The presented CMOS LNA offers a noise figure better than 3.3 dB up to 970 MHz while drawing only 3.4 mA from a 3.0 V supply. The circuit employs a topology without on-chip inductors and does not require any tuning or trimming to achieve the performance. The amplifier provides a gain of 14.8 dB in a 700 MHz wide band and has a gain of 9 dB at 900 MHz. The input IP3 is -4.7 dBm. The reverse isolation is higher than 41 dB, making it fit for insertion in a CMOS low-IF receiver.