Theoni Alexoudi

All-Optical T-Flip-Flop Using a Single SOA-MZI-Based Latching Element

The authors demonstrate a novel all-optical T-flip-flop (TFF) layout utilizing a single optical latching element that comprises an integrated semiconductor optical amplifier and Mach-Zehnder inteferometer and a feedback loop. Experimental proof-of-concept verification is presented at 8 Mb/s using off-the-shelf bulk components and a fiber-based feedback implementation. The proposed TFF architecture requires the minimum number of active components and just a single toggling signal as input. Its simple circuit design is amenable with photonic integration and holds the credentials for operation at multi-Gb/s speeds.

WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known “Memory Wall” problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

Optical interconnect and memory technologies for next generation computing

We demonstrate recent advances in the area of optical RAM-based cache memory technology and in the area of optical interconnect technologies for allowing the deployment of a disintegrated computational setting where off-chip optical cache modules can be connected to cache-light Chip Multiprocessors and DRAM modules. We report on recent experimental results obtained within the FP7 project RAMPLAS and we discuss the disintegration roadmap relying on optical PCB technologies and Si-integrated AWGR and transceiver chips pursued within the recently started project ICT-STREAMS. Finally, we demonstrate the application of optical memory setups in routing applications by proposing optical CAM memories towards the implementation of complete ultra-fast routing look-up tables directly in the optical domain.

Fabrication of high-contrast waveguide amplifiers in erbium doped potassium double tungstates

High-contrast waveguides in crystalline potassium double tungstates pave the road towards compact and efficient on-chip amplifiers. In this work, the design and fabrication of erbium doped high contrast potassium double tungstates waveguides will be described.

Optical RAM-enabled cache memory and optical routing for chip multiprocessors

In this article, we review our recent work in WDM-enabled optical RAM bank architectures and their optical all-passive peripheral modules that form a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and we report on recently integrated InP-optical memory cells as the fundamental building blocks.

Optical RAM row access using WDM-enabled all-passive row/column decoders

Towards achieving a functional RAM organization that reaps the advantages offered by optical technology, a complete set of optical peripheral modules, namely the Row (RD) and Column Decoder (CD) units, is required. In this perspective, we demonstrate an all-passive 2×4 optical RAM RD with row access operation and subsequent all-passive column decoding to control the access of WDM-formatted words in optical RAM rows. The 2×4 RD exploits a WDM-formatted 2-bit-long memory WordLine address along with its complementary value, all of them encoded on four different wavelengths and broadcasted to all RAM rows. The RD relies on an all-passive wavelength-selective filtering matrix (λ-matrix) that ensures a logical ‘0’ output only at the selected RAM row. Subsequently, the RD output of each row drives the respective SOA-MZI-based Row Access Gate (AG) to grant/block the entry of the incoming data words to the whole memory row. In case of a selected row, the data word exits the row AG and enters the respective CD that relies on an allpassive wavelength-selective Arrayed Waveguide Grating (AWG) for decoding the word bits into their individual columns. Both RD and CD procedures are carried out without requiring any active devices, assuming that the memory address and data word bits as well as their inverted values will be available in their optical form by the CPU interface. Proof-of-concept experimental verification exploiting cascaded pairs of AWGs as the λ-matrix is demonstrated at 10Gb/s, providing error-free operation with a peak power penalty lower than 0.2dB for all optical word channels.