Stéphane Adriaensen

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFETs with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250/spl deg/C

This paper deals with SOI n-MOSFET low-frequency noise measurements, analysis, and modeling from room temperature up to 250/spl deg/C. We observed the occurrence of a Lorentzian-like noise component depending on bias and temperature conditions. An engineering Lorentzian model has been validated and used in order to determine the SOI floating body effect related noise, continuously from fully- to partially-depleted regimes. General considerations about low-noise high-temperature analog circuits are discussed.

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications

The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300/spl deg/C.

Intelligent SOI CMOS integrated circuits and sensors for heterogeneous environments and applications

In this paper, we demonstrate how a simple fully-depleted SOI CMOS process can be adapted to provide a wide range of performance compatible with the realization of heterogeneous micropower, high-temperature or RF micro-systems which involve the integration of sensing, analog and digital components. High-temperature and low-voltage examples are discussed.

Low-noise SOI Hall devices

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring a wide range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs

In this paper is presented, for the first time, the design of a single-stage operational transconductance amplifier (OTA) implemented with graded-channel (GC) SOI nMOSFETs. Different design conditions were taken in account, such as similar power dissipation, transconductance over drain current ratio and die area. Comparisons with OTAs made with conventional SOI transistors are performed, showing that the GC OTAs present larger open-loop gain without degrading the phase margin, unit gain frequency and slew rate. GC OTAs can also provide the mentioned improvements while simultaneously reducing the required die area. Circuit simulations and experimental results are used to support the analysis.

Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications

In this paper. we investigate and optimize the static characteristics of NPN lateral bipolar transistors implemented in a thin-film fully-depleted SOI CMOS process for high-temperature analog applications. The basic lateral SOI bipolar device, which shows good behaviour in high-temperature circuits in spite of its relatively poor performances. is firstly described regarding its process and layout parameters, Then the concept of the graded-base bipolar transistor is introduced, This device presents significantly improved output characteristics while preserving standard current gain and CMOS process compatibility. Measurements and simulations are used to demonstrate the improvements of the breakdown voltage and the Early voltage of the bipolar device, (C) 2002 Elsevier Science Ltd. All rights reserved.

High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures

High-temperature characterization of a 0.8 /spl mu/m partially-depleted (PD) silicon-on-insulator (SOI) CMOS process is reported. The process is designed for mixed analog/digital/high-voltage applications. The measurements have been realized on n-MOSFETs, on lateral bipolar transistors and on LDMOS transistors and demonstrate the interest of the process under consideration.

Radiation Effect On Electrical Properties Of Fully-Depleted Unibond SOI MOSFETS

A radiation effect on edgeless FD accumulation mode (AM) p-channel and inversion mode (IM) n-channel MOSFETs, fabricated on UNIBOND SOI wafers, is investigated. The method of second derivative is used to determine the threshold voltages of front and back channels in the MOSFETs from the measurements of front-gate transistors only. Stronger irradiation effect on IM n-MOSFET than that on AM p-MOSFET is revealed. It has been showed, that radiation-induced positive charge in the BOX inverted back interface causes back channel creation in IM n-MOSFET but no such effect in AM p-MOSFET has been observed. It is demonstrated that small-doses have the effect of improving the quality of both interface.