Pierre Delatte

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates

This paper discusses the power saving of an LC-VCO designed on high-resistivity SOI substrates (/spl rho/ > 1000/spl Omega//spl middot/cm). It demonstrates the drastic improvement in the varactors and inductors quality factor on these substrates. It stresses on the importance of optimizing the tank inductor and the VCO for high-resistivity substrates. A 5GHz VCO designed in a 0.13/spl mu/m partially depleted SOI CMOS confirms the low-power performance with a figure-of-merit greater than 190, placing this design at the top of the state-of-the-art.

Intelligent SOI CMOS integrated circuits and sensors for heterogeneous environments and applications

In this paper, we demonstrate how a simple fully-depleted SOI CMOS process can be adapted to provide a wide range of performance compatible with the realization of heterogeneous micropower, high-temperature or RF micro-systems which involve the integration of sensing, analog and digital components. High-temperature and low-voltage examples are discussed.

Small- and large-signal RF characterization of fully-depleted accumulation-mode varactors for low-voltage LC-VCO SOI design

This paper discusses on small- and large-signal RF characterization of fully-depleted accumulation-mode varactors for low-voltage LC-VCO SOI design. This work provides a complete analysis of the evolution of K/sub v/ between small- and large-signal regimes and its consequences to the VCO design. Furthermore, several SOI devices are investigated, showing the best performances of zero voltage accumulation-mode varactors.

Noise modeling and performance in 0.15-μm fully depleted SOI MOSFET

This paper is intended to describe on one part theoretical results issued from a physical noise modeling and on the other part the noise performance of Fully Depleted (FD) SOI MOSFET of 0.15 μm gate length. In the theoretical part, the physical noise model is applied to two distinct applications; first to study the influence of the microscopic diffusion noise sources definition (located in the channel device) on the noise performance, second to check the concept of un-correlated noise sources, if one uses an input noise voltage and output drain noise current representation. In the experimental part, both bias and frequency dependences of the measured noise performances of the 0.15 μm gate length fully depleted (FD) SOI MOSFET (OKI technology) are presented, and a comparison with the results issued from the physical noise model is proposed.

High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures

High-temperature characterization of a 0.8 /spl mu/m partially-depleted (PD) silicon-on-insulator (SOI) CMOS process is reported. The process is designed for mixed analog/digital/high-voltage applications. The measurements have been realized on n-MOSFETs, on lateral bipolar transistors and on LDMOS transistors and demonstrate the interest of the process under consideration.

Analog and RF SOI Circuits for Low Power and Harsh Environment Applications

In this paper we will present two applications: high temperature electronics where SOI has a monopole for temperature between 200degC and 300degC and RF electronics where SOI has interesting performances compare to bulk. SOI is an enabling technology for high temperatures with an easier design technique. There are several SOI processes dedicated to RF applications and their main advantage will be on applications where RF, analog and digital circuits are combined in a single SoC design.

Comparison of bulk vs SOI for low power low voltage CMOS imager

To compare bulk silicon and SOI technologies in the field of CMOS image sensors, the authors have developed an analytical model of an APS circuit and applied it to the design of a 50 frames per second 512x512 pixels imager.

New Generations of Highly Integrated High Temperature DC-DC Converters

This paper presents YELLOWSTONE, a single chip, low-voltage, synchronous Buck DC-DC converter implementing a current mode PWM controller with built-in N & P-channel power MOSFETs. It aims to be used as a Point-of-Load (PoL) switched mode power supply with a maximum output current of 500mA. It generates from a typical +3.3V or +5V voltage input a lower voltage output between +0.9V and +3.3V configurable by an external resistor network. It has been specified and designed for operation at temperatures from −55°C to +225°C. Synchronous rectification increases efficiency and reduces external components count. The circuit achieves power efficiencies in excess of 90%. The chip implements a current mode PWM control which enables a fast response to line and load transient variations. A high switching frequency (1.5MHz typical with internal clock and up to 2MHz with external clock) has been selected enabling a dramatic reduction of the number and size of passive external components. The current mode control made po...

VEGA & RIGEL: New tiny high temperature adjustable voltage regulators for reduced PCB footprint and extended reliability of medium and high temperature systems

This paper presents two new tiny high-temperature adjustable voltage regulators. CHT-VEGA can regulate a 5V ±10% input voltage to an output within the range 1.1V to 3.6V and delivering up to 500mA at 225°C (junction). The output voltage is set by an external resistor divider and is maintained within +/−5% total accuracy in all load, line and temperature conditions. The second device, CHT-RIGEL, supports a wide input voltage range up to 30V; its output is adjustable between 1.8V and 24V, with up to 100mA capability at 225°C. Both chips feature a thermal shut-down with a threshold in the 250∼300°C range: the first over-temperature protection of this kind in high temperature devices. CISSOID created a new TDFP SMD package that combines tiny size and good thermal resistance. A detailed thermal characterization is presented, as well as what it means for the operating temperature, and the impact on PCB footprint and system cost. As a conclusion, will be highlighted the benefits of using such ICs rated 225°C at ...