Vincent Dessard

Fully-Depleted SOI CMOS Technology for Heterogeneous Micropower, High-Temperature or RF Microsystems

Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, our work demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under low-voltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC

Analog performance and application of graded-channel fully depleted SOI MOSFETs

The performances of the single-transistor operational transconductance amplifiers (OTAs) implemented using graded-channel (GC) and a conventional fully depleted silicon-on-insulator nMOSFETs are compared. Improvements of the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs

An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics

A device based on an asymmetric channel doping profile with the aim of reducing the inherent parasitic bipolar effects in fully depleted silicon-on-insulator (SOI) devices and improving the output characteristics is introduced. Measurements and two-dimensional simulations are used to study the device capabilities and limitations

SOI n-MOSFET low-frequency noise measurements and modeling from room temperature up to 250/spl deg/C

This paper deals with SOI n-MOSFET low-frequency noise measurements, analysis, and modeling from room temperature up to 250/spl deg/C. We observed the occurrence of a Lorentzian-like noise component depending on bias and temperature conditions. An engineering Lorentzian model has been validated and used in order to determine the SOI floating body effect related noise, continuously from fully- to partially-depleted regimes. General considerations about low-noise high-temperature analog circuits are discussed.

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs.

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lays orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mum partially-depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 times 1 bits SRAM column.

0.25 mu m fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters

The purpose of this paper is to completely describe the low and high frequency performance including microwave noise parameters of 0.25 mum Fully depleted (FD) silicon-on-insulator (SOI) devices and to compare the noise performance with 0.25 mum partially depleted (PD) devices. These FD devices present a state of the art NFmin, of 0.8 dB and high G(ass) of 13 dB at 6 GHz, at V-ds = 0.75 V, P-dc < 3 mW at 80 mum total gate width. A extrapolated maximum oscillation frequency of about 70 GHz has been obtained at V-ds, = 1 V and J(ds), = 100 mA/mm

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications

The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300/spl deg/C.

A physically-based C/sub /spl infin//-continuous model for accumulation-mode SOI pMOSFETs

In this paper, we present a unified accumulation-mode (AM) SOI MOSFET model for circuit simulation. The model is valid in all the regimes of normal operation and includes explicit expressions of the drain current and total charges which have an infinite order of continuity; therefore, smooth transitions are assured. Short-channel effects have also been accounted for. We have finally proved that our model accurately fits the transistor characteristics for effective channel lengths down to 0.7-/spl mu/m.

Ultra-low power flip-flops for MTCMOS circuits

This paper deals with new MTCMOS flip-flop architectures with high speed performance in active mode and ultra-low power dissipation in sleep mode. The use of new ultra-low leakage latch structure allows us to memorize the flip-flop state even during sleep mode and to strongly reduce the leakage in comparison with previous solutions.