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Publication
Featured researches published by Stephen Douglas Weitzel.
IEEE Journal of Solid-state Circuits | 2011
Dieter Wendel; R Kalla; James D. Warnock; R. Cargnoni; S G Chu; J G Clabes; Daniel M. Dreps; D. Hrusecky; Joshua Friedrich; Saiful Islam; J Kahle; Jens Leenstra; Gaurav Mittal; Jose Angel Paredes; Jürgen Pille; Phillip J. Restle; Balaram Sinharoy; G Smith; W J Starke; S Taylor; J. A. Van Norstrand; Stephen Douglas Weitzel; P G Williams; Victor Zyuban
This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm die, employing 1.2B transistors in a 45 nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 m DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning.
IEEE Journal of Solid-state Circuits | 2009
Steven C. Chan; Phillip J. Restle; Thomas J. Bucelot; John Samuel Liberty; Stephen Douglas Weitzel; John M. Keaty; Brian Flachs; Richard P. Volant; Peter Kapusta; Jeffrey S. Zimmerman
Resonant clocking techniques show promise in reducing global clock power and timing uncertainty (skew and jitter). By resonating the large global clock capacitance with an inductance, the energy used to charge the clock node each period can be recycled within the LC tank network, resulting in lower clock power. Additional power savings are realized by reducing the strength of clock drivers because only losses need to be overcome at resonance. Skew and jitter are improved due to the bandpass characteristic of the LC network and the use of fewer clock buffering stages. We describe how the Cell Broadband Engine (Cell BE) processor is experimentally transformed to have a resonant-load global clock distribution similar to the one in (Chan et al., 2004).
Archive | 1994
Patrick Maurice Bland; Richard Gerard Hofmann; Dennis Lee Moeller; Suksoon Yong; Moises Cases; Lance M. Venarchick; Stephen Douglas Weitzel
Archive | 2005
Chiaki Takano; Stephen Douglas Weitzel
Archive | 1980
Erich Berndlmaier; Jack A. Dorler; Joseph Michael Mosley; Stephen Douglas Weitzel
Archive | 1982
Jack A. Dorler; Joseph Michael Mosley; Stephen Douglas Weitzel
Archive | 2004
Mack W. Riley; Daniel Lawrence Stasiak; Michael Fan Wang; Stephen Douglas Weitzel
Archive | 1999
Gilles Gervais; David G. Caffo; James Nolan Hardage; Stephen Douglas Weitzel
Archive | 2002
Joachim Gerhard Clabes; Ronald Nick Kalla; Stephen Douglas Weitzel
Archive | 2000
Gilles Gervais; Stephen Douglas Weitzel