Steven C. Nash

Learning from native defects on EUV mask blanks

Defects in the EUV mask blank are one of the largest hurdles to achieving manufacturing readiness of EUV masks. For defect-free masks, the obvious approach is to order blanks that do not have defects or to shift the pattern so that remaining defects do not create a printed defect on wafer. The approach during development should be different. At this learning phase, it is wise to study the defects as they occur naturally on the EUV mask blank. This paper outlines a comprehensive approach to building a mask specifically to showcase the native defects so that they can be studied and repairs can be attempted. The method applied to mask build, defect inspection and characterization will be reviewed in detail. Printability of the mask defects of interest are characterized using both wafer printing and EUV microscope data. Repairs are attempted and characterized. In the end, the impact of native defects is discussed along with the viability of various repair methods.

Using pattern shift to avoid blank defects during EUVL mask fabrication

Extreme Ultraviolet Lithography (EUVL) is the leading candidate for next generation lithography. EUVL has good resolution because of the shorter wavelength (13.5nm). EUVL also requires a new and complicating mask structure. The blank complexity and substrate polishing requirements result in defects that are difficult to eliminate or repair. Due to these challenges, shifting the pattern so that absorber covers the multilayer defects is one option for mitigating the multilayer defect problem. We investigated the capability and effectiveness of pattern shifting using authentic layouts. The rough indication of, “how many of what size defects are allowable”, is shown in this paper based on the margin for the 11nm HP pattern. Only the twenty 300nm-sized defects are allowable for current location accuracy of the blank inspection and writing tools. On the other hand, sixty70nm-sized defects are allowable for the improved location inaccuracy. Furthermore we exercised the full process for pattern shift using a leading-edge 50 keV e-beam writer to confirm feasibility and it was successfully performed.

Next-generation lithography mask development at the NGL Mask Center of Competency

Mask fabrication is one of the difficult challenges with all Next Generation Lithography (NGL) technologies. X-ray, e-beam projection, and ion-beam projection lithography all use some form of membrane mask, and extreme ultraviolet (EUV) lithography uses a reflective mask. Despite some differences, the various mask technologies share some common features and present similar fabrication difficulties. Over the past several years, the IBM Advanced Mask Facility (AMF) has focused on the fabrication of x-ray masks. Several key accomplishments have been demonstrated including fabricating masks with critical dimensions (CD) as small as 75 nm, producing line monitor masks in a pilot line mode to evaluate mask yields, and fabricating masks to make working microprocessors with the gate level defined by x-ray lithography. The experience on fabricating 1X x-ray masks is now being applied to the other NGL mask technologies. Progress on membrane and absorber materials can be applied to all the technologies, and patterning with advanced e-beam writing with chemically amplified resists utilizes learning from writing and baking on x-ray membrane masks.

High-Accuracy Defect-Free X-Ray Mask Technology

There are many material and processing options for building highly accurate defect-free X-ray masks that meet the 0.25-µ m and smaller lithography groundrules. IBMs path and rationale for reducing the key mask parameters of image size, image placement and defects is covered. For image size resolution and control, high voltage e-beam lithography (greater then 50 kV) is the preferred technique for X-ray masks. For tighter image placement control, special writing schemes that reduce the e-beam lithography systematic and random placement errors must be used. Special absorber electroplating conditions and thermal controls were implemented to control process-induced distortion. For tight defect control, identifying and eliminating sources of defect is key. Clearly, for IBM, most of the defect sources were process rather than foreign material related. Our defect reduction work has resulted in the fabrication of a fully functional 64-Mb DRAM (single chip) mask.

Fabrication of 64-Mb DRAM using x-ray lithography

This paper describes results achieved from the fabrication of 64Mb DRAM chips using x-ray lithography for the gate level. Three lots were split at the gate level for exposure with either Micrascan 92 at IBMs Advanced Semiconductor Technology Center (ASTC) or x-ray at the Advanced Lithography Facility (ALF) containing a Helios super-conducting storage ring and a Suss stepper. The x-ray mask was fabricated at MMD (Microlithographic Mask Development Facility) as a two-chip mask containing one chip which had zero defects. To achieve adequate overlay performance between the x-ray exposed gate level and previous optically- printed levels, the mask was fabricated with an intentional magnification correction. The alignment scheme for both Suss and Micrascan was first order to an ASM zero level, and second order to each other. Results from the first lot show 90% of the chips tested achieved a +/- 140 nm target for the Suss to Micrascan overlay. Critical dimension control (across wafer and across chip) was measured and found to be comparable between Suss and Micrascan. Electrical performance was comparable to the optical wafers. Chips were fabricated with zero defects in many of the 1 Mb segments. There were also x-ray fabricated chips which demonstrated 63 Mb addressable bits.

EUV mask black border evolution

The black border is a frame created by removing all the multilayers on the EUV mask in the region around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a wafer. Papers have documented its effectiveness. As the technology transitions into manufacturing, the black border must be optimized from the initial mask making process through its life. In this work, the black border is evaluated in three stages: the black border during fabrication, the final sidewall profile, and extended lifetime studies. This work evaluates the black border through simulations and physical experiments. The simulations address concerns for defects and sidewall profiles. The physical experiments test the current black border process. Three masks are used: one mask to test how black border affects the image placement of features on mask and two masks to test how the multilayers change through extended cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images and simulated wafer effects. By evaluating the black border from both a mask making perspective and a lifetime perspective, we are able to characterize how the structure evolves. The mask data and simulations together predict the performance of the black border and its ability to maintain critical dimensions on wafer. In this paper we explore what mask changes occur and how they will affect mask use.

Development and Characterization of a New Low Stress Molybdenum Silicide Film for 45 nm Attenuated Phase Shift Mask Manufacturing

As optical lithography is extended for use in manufacturing 45 nm devices, it becomes increasingly important to maximize the lithography process window and enable the largest depth of focus possible at the wafer stepper. Consequently it is very important that the reticles used in the wafer stepper be as flat as possible. The ITRS roadmap requirement for mask flatness for 45 nm node is 250 nm. To achieve this very tight reticle flatness requirement, the stress of each film present on the mask substrate must be minimized. Another key reticle specification influenced by film stress on the mask blank is image placement. In this paper, we will describe the development and detailed characterization of a new low stress Molybdenum Silicide (MoSi) film for use in manufacturing 45 nm node critical level attenuated phase shift masks to be used in 193 nm immersion lithography. Data assessing and comparing the cleaning durability, mask flatness, image placement, Critical Dimension (CD) performance, dry etch properties, phase performance, and defect performance of the new low stress MoSi film versus the previous industry standard A61A higher stress MoSi attenuator film will be described. The results of our studies indicate that the new low stress MoSi film is suitable for 45 nm mask manufacturing and can be introduced with minimal changes to the mask manufacturing process.

Stability and stiffness characteristics of the national x-ray mask standard

Finite element analyses have been performed to investigate the stability and stiffness characteristics of the ARPA-NIST National X-ray Mask Standard. The use of different materials (such as silicon carbide and Pyrex) for the support ring has been studied to identify the effects on the maximum in-plane mounting distortions (within a 50 mm by 50 mm patterned area). Additional finite element calculations have been completed to determine the out-of-plane distortions (or bowing) of the mask due to the fabrication process. Parametric studies have been performed to identify the stiffness characteristics of the mask as the overall ring thickness is reduced while the wafer thickness is increased. Results show how various design parameters can be controlled to repeatedly fabricate masks that fulfill requirements for sub-0.13 micrometer technology.

Status of x-ray mask inspection and repair

The status of x-ray mask inspection and repair at the IBM Advanced Mask Facility is presented. Defect classification and sources are presented along with some preliminary results from a defect printing study done at the Advanced Lithography Facility.