Jed H. Rankin

Improving the power-performance of multicore processors through optimization of lithography and thermal processing

It is generally assumed that achieving a narrow distribution of physical gate length (Lpoly) for the poly conductor layer helps improve power performance metrics of modern integrated circuits. However, in advanced 90 nm technologies, there are other drivers of chip performance. In this paper we show that a global optimization of all variables is necessary to achieve the optimum performance at the lowest leakage. We will also describe how systematic physical gate-length variation can improve core matching in multicore designs.

Using pattern shift to avoid blank defects during EUVL mask fabrication

Extreme Ultraviolet Lithography (EUVL) is the leading candidate for next generation lithography. EUVL has good resolution because of the shorter wavelength (13.5nm). EUVL also requires a new and complicating mask structure. The blank complexity and substrate polishing requirements result in defects that are difficult to eliminate or repair. Due to these challenges, shifting the pattern so that absorber covers the multilayer defects is one option for mitigating the multilayer defect problem. We investigated the capability and effectiveness of pattern shifting using authentic layouts. The rough indication of, “how many of what size defects are allowable”, is shown in this paper based on the margin for the 11nm HP pattern. Only the twenty 300nm-sized defects are allowable for current location accuracy of the blank inspection and writing tools. On the other hand, sixty70nm-sized defects are allowable for the improved location inaccuracy. Furthermore we exercised the full process for pattern shift using a leading-edge 50 keV e-beam writer to confirm feasibility and it was successfully performed.

EUV mask cleans comparison of frontside and dual-sided concurrent cleaning

The cleaning requirements for EUV masks are more complex than optical masks due to the absence of available EUVcompatible pellicles. EUV masks must therefore be capable of undergoing more than 100 cleaning cycles with minimum impact to lithographic performance. EUV masks are created on substrates with 40 multilayers of silicon and molybdenum to form a Bragg reflector, capped with a 2.5nm-thick ruthenium layer and a tantalum-based absorber; during usage, both ruthenium and absorber are exposed to the cleaning process. The CrN layer on the backside is used to enable electrostatic clamping. This clamp side must also be free of particles that could impact printing and overlay, and particles could also potentially migrate to the frontside and create defects. Thus, the cleaning process must provide decent particle removal efficiencies on both front- and backside while maintaining reflectivity with minimal surface roughness change. In this paper, we report progress developing a concurrent patterned-side and clamped-side cleaning process that achieves minimal reflectivity change over 120 cleaning cycles, with XPS and EDS indicating the presence of ruthenium after 125 cleaning cycles. The change in surface roughness over 100 cleaning cycles is within the noise (0.0086nm) on a mask blank, and SEM inspection of 100nm and 200nm features on patterned masks after undergoing 100 cleaning cycles show no indications of ruthenium pitting or significant surface damage. This process was used on test masks to remove particles from both sides that would otherwise inhibit these masks from being used in the scanner.

Exploring EUV mask backside defectivity and control methods

The backside of photomasks have been largely ignored during the last several decades of development, with the exception of avoiding gross damage or defects, as almost all problems are far enough out of the focal plane to have minimal effect on imaging. Since EUV masks are reflective, and the column is held in a vacuum, scanners have been designed to utilize electrostatic chucking. With the chucking system for EUV, the requirements for the backside of the mask must be redefined to integrate concerns in substrate design, mask manufacturing, and usage. The two key concerns with respect to an electrostatic chuck are defects and durability. Backside defects can affect imaging, while potentially damaging or contaminating the tool, the mask, or even subsequently used masks. Compromised durability, from either usage or cleaning, can affect the ability of the chuck to hold the mask in place. In this study, these concerns are evaluated in three stages: minimizing defects created during mask fabrication, actions taken upon discovery of defects, and durability of the backside film with continued cleans and chucking. Data incorporated in this study includes: sheet resistance, film thickness, and optical inspection images. Incorporating the data from the three stages of fabrication, disposition, and lifetime will help us define how to structure backside EUV mask handling during mask manufacture and indicate what further solutions are needed as EUV technology transitions into manufacturing.

Optimization of silicon technology for the IBM system z9

IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9TM processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9TM to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.

Investigating into mask contribution to device performance and chip functionality

Device performance and functionality can be impacted by many factors, both physical and electrical. Close interaction between the lithographer and mask maker is useful in the deconvolution of the mask contributions to device speed and functionality. Across plate image size variation, linearity, orientation and proximity effects (both local and global) influence the Across Chip Linewidth Variation (ACLV). ACLV, in turn, has a strong correlation to overall device performance. Several situations in which integrated circuit functionality and performance were correlated to mask systematics will be presented along with resolution of the described issues. Methodologies for separating the mask components from the wafer level process components will also be discussed. Mask specifications are often derived by simply scaling the previous technology, rather than basing the specifications on technical requirements. A methodology will be derived which links technological device specifications and the anticipated mask exposure conditions to the required mask specifications.

Two-dimensional mask effects at the 14 nm logic node

At the 14 nm logic node, significant lithographic changes relative to previous technologies are needed to resolve smaller features with increased fragmentation in mask design and increased use of sub-resolution assist features. Extending the application of 193 immersion lithography for further generations requires not only continued reduction of traditional sources of variation but investigation into and quantification of the impact of completely new ones, such as mask twodimensional (2D) variability. To improve the overall lithography model accuracy, two-dimensional (2D) data from the mask is required to complete a mask model with an optimal wafer response. This paper characterizes and assesses the importance of 2D mask effects on thin opaque MoSi on glass (OMOG) masks. Methodologies for characterizing corner rounding in terms of corner rounding radius and contact area are presented. Optical mask 2D measurements and wafer print results are summarized.

Cr migration on 193nm binary photomasks

A new type of chrome-on-glass (COG) photomask defect was observed in 2006. Absorber material migrated into vias on dark field masks, partially obscuring the incident 193nm light and thereby causing the imaged photoresist to be underexposed. Through detailed characterization of new and defective photomasks and their histories it was determined that the migration is not caused by any unusual line events or faulty mask handling procedures. Rather, it is an inevitable result of mask use under specific conditions. Four essential elements have been identified: the presence of Cr, 193nm light exposure, charge, and water vapor and their roles elucidated through modeling studies and existing literature. We have reproduced Cr migration in the laboratory, demonstrating that these four elements are necessary and sufficient for this type of defect to occur. The only way to avoid Cr migration is to avoid reactions with water vapor.

Your worst nightmare: inspection of aggressive OPC on 14nm masks with emphasis on defect sensitivity and wafer defect print predictability

To prevent catastrophic failures during wafer manufacturing, mask manufacturers employ sophisticated reticle inspection systems to examine every image on every reticle to identify defects. These advanced systems inspect at resolutions typically 3x higher at the reticle-plane than advanced wafer scanners; thus enabling them to detect the small defects necessary to ensure reticle quality. The most thorough inspection is done using a reticle-to-database comparison that ensures the reticle pattern matches the design pattern. For high defect sensitivity, the database must be carefully modeled to exactly match the reticle pattern. Further, sub-resolution OPC shapes are often at the limit of the mask manufacturing process, which adds subtle variations on such shapes across the reticle. These modeling errors and process variations can cause high numbers of unwanted detections, thereby limiting inspection system defect detection sensitivity.[1] OPC designs are expected to become more aggressive for future generations and may stress the performance of current reticle inspection systems. To systematically assess the capability of various inspection approaches and identify needed areas for improvement, a new “Nightmare” test reticle has been designed by IBM. The test reticle contains various sizes and shapes of sub-resolution features that might appear on reticle generations from today’s 22nm to future 7nm. It also contains programmed defects to assess defect detection capability of current and future generation inspection systems. This paper will discuss the design of the “Nightmare” test reticle, and the inspection results of the current generation reticle inspection methods with emphasis on both inspectability and defect sensitivity. The subresolution features will be ranked according to importance for advanced OPC design. The reticle will also be evaluated using wafer print simulation so lithographic impact of features and defects can be measured and compared against inspection approaches and results.

Mask process characterization of multiresolution writing

Multiresolution writing refers to a technique used to simplify the data in one or more of the write passes performed by a vector-based e-beam writer while maintaining the detail in at least one of the remaining layers. This technique has been demonstrated to reduce the total shot count by as much as 30% with minimal predicted impact to the mask features formed, and no predicted impact to the wafer lithographic results. We investigate the impact of this technique on the mask manufacturing process. Specific mask parameters investigated include critical dimension uniformity, critical dimension proximity and linearity effects, line edge roughness, and mask inspectibility. Additional considerations include the applicability of this technique to existing mask designs as well as next generation RET solutions. This characterization identifies an operating regime where shot savings can be realized while still maintaining acceptable mask quality.