Robert J. Gauthier

A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection

We present a novel RC-triggered, MOSFET-based power clamp for on-chip ESD protection. The cascaded PFET feedback technique is introduced. As with other feedback techniques, only a very small time constant is required for the RC trigger circuit which results in reduced capacitor area and reduced leakage at power-up. If mistriggering occurs, it is self-corrected with this dynamic feedback technique.

Reliability aspects of gate oxide under ESD pulse stress

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

Latchup in CMOS technology

This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1–5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies

We explore the effect of layout factors on the turn-on time of silicon controlled rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a very fast transmission line pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results

VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing

Very fast transmission line pulse (VF-TLP) systems described in the literature are time domain reflection (VF-TDR) configurations. Using other TLP configurations, VF-TLP systems can provide new capabilities. A wafer level Kelvin probe system was derived from VF-time domain transmission (VF-TDT). A test fixture board (TFB) using VF-time domain reflection and transmission (VF-TDRT) enables VF-TLP package level testing.

High-current transmission line pulse characterization of aluminum and copper interconnects for advanced CMOS semiconductor technologies

High-current phenomena and electrostatic discharge (ESD) in both aluminum and copper interconnects using transmission line pulse (TLP) testing are reported. Critical current density-to-failure, J/sub crit/, is evaluated as a function of pulse width for both wire and via structures. Experimental results demonstrate that copper-based interconnects have superior ESD robustness compared to aluminum-based interconnects.

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90nm CMOS ASICs

We report the characterization of diode and bipolar triggered SCRs with VFTLP measurements and product ESD testing. A dual base Darlington bipolar triggered SCR (DbtSCR) in a triple well structure is demonstrated to provide 4 KV HBM, 300 V MM and 1000 V CDM protection for 90 nm ASIC I/Os. A very fast turn-on time of 460 ps was measured for the DbtSCR, compared to 8 ns for a diode triggered SCR.

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-/spl mu/m CMOS technology

Historically, the failure mode of the nMOS/lateral n-p-n (L/sub npn/) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-/spl mu/m CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I/sub D/-V/sub G/ and I/sub G/-V/sub G/ measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I/sub f/ of the nMOS/L/sub npn/ are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.