Naomi Yoshida

15nm-W FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET_INV-normalized G_M,SAT,INT of 6.7 nm.mS/μm, the Si_0.3Ge_0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

Chemical studies of CVD Cu deposited on Ta and TaN barriers under various process conditions

Contamination in the matrix of CVD copper films and at the interface between CVD copper films and barrier layers has been characterized using XPS, SIMS, XRD and RGA. Contamination in the CVD copper matrix has been found to increase with increasing precursor flow rate and with decreasing wafer temperature. Interfacial contamination has been investigated in an attempt to quantitatively define acceptable levels of contamination and ultimately reduce the effect of these contaminants on the integrated film stack. Sputtered copper flash layers for CVD copper deposition are also shown as highly effective for reducing the levels and effects of incorporated contamination.

High-k/metal gate stacks in gate first and replacement gate schemes

In this work, representative high-k/metal gate MOS-capacitor stacks were fabricated in both gate first and replacement gate integration schemes. Aluminum- and lanthanum- based cap layers (both widely accepted as Vt tuning cap layers in the industry), in addition to TiN metal gate, can tune the effective workfunction towards PMOS and NMOS, respectively. Varying Ti:N stoichiometry in TiN can induce >250mV change in TiN workfunction. 1 volt separation between NMOS and PMOS was achieved by screening various workfunction materials in replacement gate scheme. Substrate modification during the growth of aluminum was key to achieving void-free aluminum gap fill in narrow gate trenches.

Highly scalable bulk FinFET Devices with Multi-V T options by conductive metal gate stack tuning for the 10-nm node and beyond

A scalable multi-VT enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-VT is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack Tinv, JG, DIT and reliability as well as the device performance are shown to be unaffected by the multi VT process.

Influence of diffusion barriers on the nucleation and growth of CVD Cu for interconnect applications

Abstract Nucleation and growth behavior of Cu influence strongly the macroscopic properties of the resultant films. In this work the nucleation of CVD Cu on different underlayer materials is studied. It is found that nucleation on bare diffusion barrier surfaces leads to island growth and, therefore, bad wetting and adhesion. An enrichment of F, O and carbon was found at the interface between the CVD Cu film and the diffusion barrier. However CVD Cu deposited on top of Ta with a 200-A PVD Cu layer on top results in good wetting. CVD Cu films grown on a PVD Cu layer expose a highly preferred 〈111〉 orientation. In this case SIMS analysis reveals a comparably low concentration of oxygen, carbon and flourine at the interface region between the CVD Cu and the barrier. These observations shed light on relevance of surface conditions for the CVD Cu deposition process. They significantly affect both film adhesion and crystal orientation, which are crucial for the use of CVD Cu as interconnect material.

Nitride passivation of the interface between high-k dielectrics and SiGe

In-situ direct ammonia (NH3) plasma nitridation has been used to passivate the Al2O3/SiGe interfaces with Si nitride and oxynitride. X-ray photoelectron spectroscopy of the buried Al2O3/SiGe interface shows that NH3 plasma pre-treatment should be performed at high temperatures (300 °C) to fully prevent Ge nitride and oxynitride formation at the interface and Ge out-diffusion into the oxide. C-V and I-V spectroscopy results show a lower density of interface traps and smaller gate leakage for samples with plasma nitridation at 300 °C.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

Metal gate work function modulation by ion implantation for multiple threshold voltage FinFET devices

FinFET has emerged as a device structure to enable the device scaling at and beyond the 22nm technology node due to increasingly stringent demands for maximum device speed, lower leakage current and control of random dopant fluctuation effects. High-k dielectric (Hik)/metal gate (MG) technology makes it feasible to obtain improved Effective Oxide Thickness (EOT) scaling and reduced leakage. Replacement metal gate (RMG) flows have been used for high performance logic volume production at and beyond 45nm node [1]. Precise threshold voltage (Vt) control and multiple Vt are required for FinFET device architectures for future devices. This paper proposes an ion implantation approach for modulating metal gate work function for both n-metal and p-metal gate used in a HiK last and replacement gate process. This approach offers simplified integration flow where no additional mask is needed and resist mask can be used. The effective work function (eWF) was measured along with the EOT and Gate Leakage (Jg). Stress Induced Leakage Current (SILC) method was used for testing HiK stack reliability. The results showed up to 200mV eWF modulation by ion implantation with fine control and without EOT and Jg degradation. The effect of implant species and dose on the eWF was studied in this paper. SIMS analysis of HKMG stack on the blanket wafer was used to determine the dopant distribution and explore the possible mechanism for metal gate work function modulation by ion implantation.