Atif Noori

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Novel metal gates for high κ applications

The development of gate systems suitable for high κ dielectrics is critical to the advancement of complementary metal-oxide-semiconductor (CMOS) devices. Both the effective work function and material stability are key parameters to these systems. A systematic study of metal gates of the composition HfxSi1-x (0.25 ≤ x ≤ 1) is demonstrated here, including XPS, XRD and four point probe measurements. The effective work function of each material is evaluated and it is shown that it can be tuned from 4.5 to less than 4.0 eV. Suitable work functions for n-channel metal-oxide-semiconductor applications (4.05 ± 0.2 eV) were achieved using hafnium rich compositions; however, XPS and diffraction measurements confirmed that these materials demonstrated a high propensity to oxidise, causing the reduction of the underlying oxides, making them unsuitable for commercial application.

Replacement metal gate extendible to 11 nm technology

This paper describes novel Co-Al metal fill capable of filling sub-10nm trenches. Co-Al fill shows advantages in threshold voltage (VTH) variation. The conductivity of the fill was evaluated using a Co-Al alloy conductance model. By demonstrating better VTH variability, superior conductivity and gap fill, Co-Al shows extendibility to the 11nm metal gate and beyond.

Threshold voltage tuning by metal gate work function modulation for 10 nm CMOS integration and beyond

This paper describes a novel scheme of metal gate integration to achieve precise threshold voltage (VTH) control and multiple VTH, by using metal composition and ion implantation (I/I) into work function metal (WFM). Moreover, WFM full fill is demonstrated with in situ barrier metal to satisfy the conductance requirement of sub-10 nm node gate.

Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.

Devices with High-k Last Replacement Metal Gate Technology A. Veloso, S. A. Chew, Y. Higuchi, L.-Å. Ragnarsson, E. Simoen, T. Schram, T. Witters, A. Van Ammel, H. Dekkers, H. Tielens, K. Devriendt, N. Heylen, F. Sebaai, S. Brus, P. Favia, J. Geypen, H. Bender, A. Phatak, M. S. Chen, X. Lu, S. Ganguli, Y. Lei, W. Tang, X. Fu, S. Gandikota, A. Noori, A. Brand, N. Yoshida, A. Thean, and N. Horiguchi IMEC, assignee at IMEC from Panasonic, Applied Materials Belgium NV, Kapeldreef 75, 3001 Leuven, Belgium; Applied Materials Inc., 3050 Bowers Ave., Santa Clara, CA 95054, USA Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be

High-k Gate Stack: Improved Reliability through Process Clustering

Introduction High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS since its adoption at the 45nm node [1]. A typical HK stack consists of the SiO2 interfacial layer (iL) followed by a nitrided and annealed HK dielectric. Both the nitridation and anneal results in an increased dielectric constant and improved HK and stability. It has been demonstrated in numerous papers that the quality of the HK bulk material and the interface with the iL plays a critical role in transistor’s reliability degradation. This degradation, generally due to electron trapping in the HK bulk and/or at the iL/HK interface, is quantified by Bias-Temperature Instability (BTI) which closely correlates to CV hysteresis [2]. Because of such reliability degradation concerns, clustering of the different HK stack process chambers in one single tool is critical in eliminating layer exposure to fab ambient that could result in HK bulk and interface quality degradation.