Yogesh Darwhekar

A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF

A single-chip GPS receiver with a low-IF heterodyne RF front-end includes a LNA, image-reject IQ mixers, a passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, a /spl Delta//spl Sigma/ ADC, and a digital IF-filter. The receiver dissipates 60 mA at 1.4 V and achieves a NF of 2 dB and out-of-band IIP3 of 5 dBm.

A 45nm CMOS near-field communication radio with 0.15A/m RX sensitivity and 4mA current consumption in card emulation mode

Near Field Communication (NFC) is an emerging technology that is penetrating the mobile phone market rapidly. Compliance to multiple NFC standards [1-3] requires designs to support wide dynamic range of field (0.15 to 12A/m), multiple data rates (1.65 to 848Kb/s), various modulation transition times (0.01 to 8usec), wide range of modulation indices (8 to 100%) and line coding techniques (Manchester, NRZ, Modified Miller and PPM). Also, support for small antenna size and very low power card emulation (tag) operation results in additional design constraints. The solution described here integrates all the NFC functions on a multi-IP connectivity SOC in 45nm CMOS.

A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain

We describe the design of a fifth order opamp-RC filter in a 65nm digital CMOS process. Designed for a WLAN receiver chain, the baseband filter has a bandwidth of 9MHz and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements. Measurements show a 24 dB adjacent channel attenuation and an out-of-band IIP3 of 33 dBm. The complete filter consumes 9.5mA from a 1.3V supply and occupies an area of 0.46mm2.

IQ mismatch compensation using time domain signal processing: A practical approach

In recent times, analysis of transceiver RF front-end analog impairments and their compensation using digital signal processing techniques have drawn increasing interest. Analysis and calibration of frequency dependent and frequency independent IQ imbalance (FD-IQI & FI-IQI) are explored in this paper. In order to reduce implementation complexity, we propose sequential compensation rather than joint compensation of FD-IQI and FI-IQI. A low-complexity technique for compensation of FD-IQI in time-domain is presented. Fundamental limit on estimation accuracy of FI-IQI parameters is derived in the presence of uncompensated FD-IQI. Impact of the proposed technique on packet-error-rate (PER) performance of a IEEE 802.11g receiver is demonstrated via silicon measurements.