Suk-pil Kim

Low power operating bipolar TMO ReRAM for sub 10 nm era

The bottle neck of ReRAM (Resistive RAM) for post-NAND storage application is high operational current [1,2]. Herein, we report a method to acquire low operational currents from a hetero structure ReRAM (AlOx/TiOx). The mechanism study of the hetero structure ReRAM reveals that the AlOx layer as a tunnel barrier is critical for switching, and thus switching parameters are governed by the properties of the AlOx layer. By tuning tunnel oxide properties along with adopting 5 nm sized “Dash BE” [3], operational currents of ≤ 10 µA have been achieved from this hetero structure device.

Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

A new type of memory, paired FinFET charge trap memory is reported. It consists of two split silicon fins and insulator between them. Two channels are formed on the outer surface of silicon so doubled integration density can be achieved. We successfully fabricated paired FinFET SONOS devices. It shows good program and erase characteristics. Independent programming on each storage nodes is demonstrated. The circuit configuration for NAND flash application is also proposed

Transient-current measurement of the trap charge density at interfaces of a thin-film metal∕ferroelectric∕metal structure

A method providing estimation of the trap density at metal∕ferroelectric interfaces of a depleted ferroelectric film located between back-to-back Schottky barriers has been developed. The method is based on the recharge of interface traps induced by external bias pulse applied to the metal∕ferroelectric∕metal structure. It is shown that the transient current under bias pulse can be controlled by the trap recharge on the reverse-biased interface. Using the method, the trap charge density on interfaces of the Pt∕PZT∕Ir(Ti∕SiO2∕Si) capacitor was found from transient-current measurements to be two orders of magnitude less than the remnant polarization of PbZrxTi1−xO3 film.

Improvement of retention loss in Pb(Zr,Ti)O3 capacitors using Ir∕SrRuO3 top electrodes

We investigated the retention behavior of Pb(Zr,Ti)O3 (PZT) capacitors with Ir∕SrRuO3 (SRO) top electrodes. The capacitors with Pt and Ir∕IrO2 top electrodes were also prepared for comparison. The opposite state retention characteristic of the PZT capacitor was significantly improved by using an Ir∕SRO top electrode structure. The nonvolatile polarization of the opposite state retention was kept at 96% of its initial value even after a 100h baking test at 150°C, while those of Pt and Ir∕IrO2 were 36 and 59%, respectively. The retention enhancement is attributed to the effective inhibition of defect generation on the interface between PZT and SRO.

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

We fabricated trench PbZrxTi1-xO3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm2 remnant polarization

Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

Multi-bit vertical structure NAND (VsNAND) flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10 nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND flash array cells with TANOS (TaN/Al2O3/SiN/SiOx/Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND flash application.

Trap Charge Density at Interfaces of MOCVD Pt(Ir)/PZT/Ir(Ti/SiO 2 /Si) Structures

A method providing estimation of the trap density at metal/ferroelectric interfaces of a depleted ferroelectric film located between back-to-back Schottky barriers has been developed. The method is based on the recharge of interface traps induced by external bias pulse applied to the metal/ferroelectric/metal structure. It is shown that the transient current under bias pulse can be controlled by the traps recharge on the reverse-biased interface. Using the method, the trap charge density on interfaces of MOCVD Pt/PZT/Ir(Ti/SiO 2 /Si) and Ir/PZT/Ir(Ti/SiO 2 /Si) capacitors were found from transient current measurements.

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

The Investigation of Ferroelectric Domain Behavior Affected by Thin Metallic Electrode

The physical and chemical properties of metallic electrodes on Pb(Zr,Ti)O3 (PZT) are investigated by atomic force microscopy. Pt, a catalyst, tends to change itself into a dielectric oxide. Such a passive layer should cause a depolarization field driving the domain structure into the polystate. Therefore, the effective thickness of the Pt electrode becomes smaller than that of Ir electrode. Thus, we observed an opposite domain contrast around a region covered by thin Pt on PZT, which implied the failure of the screening of the depolarizing field. This multidomain configuration can cause a suppression of the remnant polarization of PZT capacitors. Also, Ir is better than Pt in regard to film smoothness, indicating that the adhesion property of Ir on PZT is superior to that of Pt on PZT. We prove it using height–height correlation function. This study is significant on the scaling issues of ferroelectric capacitors, such as the thickness limit of the electrode and the requirement for high surface smoothness of ferroelectric films.

Novel Ir–Ti Alloy Electrodes for High-Density Ferroelectric Memory Applications

An Ir-based Ir–Ti alloy was improved by controlling the interface layer between Pb(Zr,Ti)O3 (PZT) and an electrode for the high-density ferroelectric memory application. Compared with the Ir electrode, the Ir–Ti alloy electrode was resistant to oxygen annealing and the surface did not roughen much. The increase in resistivity after the annealing was also sufficiently low to maintain its feasibility as an electrode. Furthermore, Ti in the Ir–Ti alloy seemed to assist the growth of (111) grains of PZT, thus resulting in a larger 2Pr. The Ir–Ti alloy layer also acted as a seed layer for PZT. This means that we can skip the deposition of the seed layer for the purpose of good quality PZT. Furthermore, the Ir–Ti alloy is still applicable to very thin films. In ultra thin films of PZT and a bottom electrode, IrTiOx (20 nm)/IrTi (10 nm) is a good choice as the bottom electrode to conserve 2Pr as well as protect the reliability of thin PZT. This is a very different result from IrOx. It is believed that these results could provide a possibility for commercializing embedded or stand-alone FeRAM in high-density ferroelectric memory applications.