Sun-Ho Oh

Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source (C gs ) and gate-to-drain (C gd ) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency (f T ) and maximum-oscillation frequency (f max ) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

Effect of fluorine implantation on recovery characteristics of p-channel MOSFET after negative bias temperature instability stress

In this paper, the effect of fluorine implantation on the recovery characteristics of p-channel MOSFETs (PMOSFETs) after negative bias temperature instability (NBTI) stress was investigated. PMOSFETs using fluorine ion implantation (F-I/I) performed better than those without F-I/I after NBTI stress; it is thought that F-I/I can suppress the generation of permanent damage during NBTI stress. The relationship of ΔVth and ΔSS during NBTI stress and recovery showed how much permanent damage occurred. In addition, we confirmed with a 1/f noise measurement that the device with F-I/I was immune to NBTI stress in spite of a pre-existing bulk trap caused by implantation damage. Moreover, the device with F-I/I had greater activation energy than the device without F-I/I. As indicated by the results, fluorine implantation can decrease the generation of permanent damage under NBTI stress because of the stable Si–F bond.

Modeling of T-model equivalent circuit for spiral inductors in 90 nm CMOS technology

This paper presents a newly proposed T-model of spiral inductors in 90nm radio frequency (RF) CMOS technology. Inductor modeling is one of the most difficult problems facing silicon-based RF integrated circuit designers, and the inclusion of many parameters of the inductor equivalent circuit consumes a lot of time during circuit simulation. In this paper, two models of spiral inductors were simulated to compare their agreement with the measured data from 100MHz to 10GHz. The proposed T-model had less parameters than the conventional double-π model, and also showed good agreement in the RF performance of the spiral inductors, such as quality factor (Q-factor) and inductance (L). In addition, the proposed T-model had an error rate of less than 5% with the S-parameter of measured data, similar to the double-π model.

Analysis of Reliability for Different Device Type in 65 nm CMOS Technology

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond 0.18 μm CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

Effect of Uderpass Structure on Quality Factor and Breakdown Voltage in RF Inductor

In this paper, the effect of underpass structure on quality factor and breakdown voltage of octagonal inductors which were fabricated with 90 nm complementary metal-oxide-semiconductor (CMOS) technology for radio frequency integrated circuit (RFIC) was studied. It was found that quality factor and breakdown voltage of inductors with more than one metal layer for underpass showed improved properties compared to those with one metal layer. However, little change of quality factor and breakdown voltage was observed between the inductors with two and more than two metal layers for underpass. Therefore, underpasses with two metal layers are promising for RFIC designs of the octagonal inductors in 90 nm CMOS technology.

Comparative Analysis of Channel Length Dependence of NBTI and CHC Characteristics in PMOSFETs

Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.