Sung-Kyu Kwon

Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source (C gs ) and gate-to-drain (C gd ) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency (f T ) and maximum-oscillation frequency (f max ) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

Effects of High-Pressure Annealing on Random Telegraph Signal Noise Characteristic of Source Follower Block in CMOS Image Sensor

The effect of high-pressure deuterium (D) and hydrogen (H) annealing on random telegraph signal (RTS) noise characteristics of source follower (SF) block, SF, and row selector (SEL) transistors in CMOS image sensor (CIS) active pixel sensor (APS) was comparatively analyzed in depth. RTS noise characteristics of SF transistor (M1) and SEL transistor (M2) with forming gas (FG) annealing showed the smallest Δ<i>I</i>_D/<i>I</i>_D, whereas FG annealing was not efficient to reduce the RTS noise of SF block (M1 + M2). Although Δ<i>I</i>_D/<i>I</i>_D of SF block was reduced by high-pressure H₂ annealing, high-pressure D₂ annealing showed the greatest reduction in Δ<i>I</i>_D/<i>I</i>_D of SF block (M1 + M2), which was believed to attribute to the effective passivation of interface traps by the isotope effect of D. Therefore, high-pressure D₂ annealing is potentially significant for reducing RTS noise characteristics and thermal budget as well as improving device performance in CIS APS.

Effect of Nitrogen Concentration on Low-Frequency Noise and Negative Bias Temperature Instability of p-Channel Metal--Oxide--Semiconductor Field-Effect Transistors with Nitrided Gate Oxide

In this paper, the dependence of negative bias temperature instability (NBTI) and low-frequency noise characteristics on the various nitrided gate oxides is reported. The threshold voltage shift (ΔVT) under NBTI stress for thermally nitrided oxide (TNO) was greater than that of plasma nitrided oxide (PNO), whereas the slopes of ΔVT versus stress time for PNO were similar to those for TNO. The flicker noise (1/f noise) characteristic of PNO was better than that of TNO by about 1 order of magnitude, although the 1/f noise of PNO showed almost the same dependence on the frequency as that of TNO. The carrier number fluctuation model due to the trapping and detrapping of electrons in oxide traps was found to be a dominant mechanism of flicker noise. The probability of the generation of drain current random telegraph signal (ID–RTS) noise shows similar values (70–78%) for all nitrided oxides, which shows that the generation of RTS noise is not greatly affected by the nitridation method or nitrogen concentration.

Effect of fluorine implantation on recovery characteristics of p-channel MOSFET after negative bias temperature instability stress

In this paper, the effect of fluorine implantation on the recovery characteristics of p-channel MOSFETs (PMOSFETs) after negative bias temperature instability (NBTI) stress was investigated. PMOSFETs using fluorine ion implantation (F-I/I) performed better than those without F-I/I after NBTI stress; it is thought that F-I/I can suppress the generation of permanent damage during NBTI stress. The relationship of ΔVth and ΔSS during NBTI stress and recovery showed how much permanent damage occurred. In addition, we confirmed with a 1/f noise measurement that the device with F-I/I was immune to NBTI stress in spite of a pre-existing bulk trap caused by implantation damage. Moreover, the device with F-I/I had greater activation energy than the device without F-I/I. As indicated by the results, fluorine implantation can decrease the generation of permanent damage under NBTI stress because of the stable Si–F bond.

A Study of Dielectric Relaxation and Capacitance Matching of

Key analog characteristics such as dielectric relaxation and capacitance matching for Al2O3/HfO2/Al2O3 (AHA) metal-insulator-metal (MIM) capacitors were analyzed for high-performance analog circuit applications. Although the dc characteristics of AHA MIM capacitor were acceptable for analog operation, the variation of the quadratic voltage coefficient (α) under constant voltage stress (CVS) and the dielectric relaxation remained problematic. The dependence of α for AHA MIM capacitor decreased gradually under CVS and the dielectric relaxation of AHA MIM capacitor was greater than that of conventional MIM capacitor, which was due to the effect of preexisted traps in high- k dielectric. The extracted matching coefficient of AHA MIM capacitor was, however, 0.698% μm, which was low enough to be used for analog/mixed signal/radio frequency application.

{\rm Al}_{2}{\rm O}_{3}/{\rm HfO}_{2}/{\rm Al}_{2}{\rm O}_{3}

Low frequency noise has become one of the major issues for an analog mixed signal and RF (radio frequency) circuits [1]. Previous studies have extensively analyzed drain/gate bias and temperature dependence of 1/f (flicker) noise in a strong inversion region [2, 3], whereas 1/f noise in a sub-threshold region has been investigated very little. The demand for low power consumption has increased due to the development of single battery cell phones. Hence, to reduce the dynamic power consumption of CMOS circuits, threshold voltage must be scaled down without degrading circuit speed or operating logic noise margins. Although Vth scaling is limited by the off-current and static power consumption constraints, a constant substrate biasing technique is used with standard CMOS technology to improve the performance of CMOS circuits. As this technique is used in analog-integrated circuits, such as current mirror and VCO (voltage controlled oscillator), the dependence of 1/f noise characteristics on body bias need to be analyzed. In addition, the noise characteristic of MOSFETs at high temperature is important for analog circuits because the analog circuits are more sensitive to temperature [4, 5]. However, there was little study on the noise characteristics concurrently considering the body bias and temperature. In this study, 1/f noise characteristics of NMOSFET were investigated for various body bias and temperature in a sub-threshold region.

MIM Capacitors

This paper presents a newly proposed T-model of spiral inductors in 90nm radio frequency (RF) CMOS technology. Inductor modeling is one of the most difficult problems facing silicon-based RF integrated circuit designers, and the inclusion of many parameters of the inductor equivalent circuit consumes a lot of time during circuit simulation. In this paper, two models of spiral inductors were simulated to compare their agreement with the measured data from 100MHz to 10GHz. The proposed T-model had less parameters than the conventional double-π model, and also showed good agreement in the RF performance of the spiral inductors, such as quality factor (Q-factor) and inductance (L). In addition, the proposed T-model had an error rate of less than 5% with the S-parameter of measured data, similar to the double-π model.

Dependence of 1/f noise characteristics of NMOSFETs on body bias and temperature in sub-threshold region

In this paper, the dielectric relaxation and reliability of high capacitance density metal-insulator- metal (MIM) capacitors using Al2O3-HfO2-Al2O3 and SiO2-HfO2-SiO2 sandwiched structure under constant voltage stress (CVS) are characterized. These results indicate that although the multilayer MIM capacitor provides high capacitance density and low dissipation factor at room temperature, it induces greater dielectric relaxation level (in ppm). It is also shown that dielectric relaxation increases and leakage current decreases as functions of stress time under CVS, because of the charge trapping effect in the high-k dielectric. Index Terms—MIM (Metal-Insulator-Metal), AHA (Al2O3-HfO2-Al2O3), SHS (SiO2-HfO2-SiO2), charge trapping effect, dielectric relaxation

Modeling of T-model equivalent circuit for spiral inductors in 90 nm CMOS technology

To realize high-resolution pixels in the CMOS image sensor, it is necessary to reduce low-frequency noise, particularly random telegraph signal (RTS) noise of the source-follower transistor (SFT). To achieve less relative variation of drain noise current, ΔI D/I D, a metal–oxide–semiconductor field-effect transistor structure without the lightly doped drain (LDD) for the SFT transistor is proposed. Then, a comparison of RTS noise characteristics between the proposed SFT structure without LDD and the conventional SFT structure with LDD was conducted. Although the RTS noise occurrence probability of the proposed SFT structure without LDD is somewhat greater than that of the conventional SFT structure with LDD, the amplitude of relative variation of drain noise current of the proposed SFT structure is significantly less than that of the conventional SFT. Despite changes in several factors in the proposed SFT, such as effective channel length, trap depth profile in gate oxide, and random dopant fluctuation (RDF), it is believed that the change of trap depth profile is a primary factor for the improved RTS characteristic. Therefore, the proposed SFT is highly desirable for the high-resolution CMOS image sensor.

Characterization of Dielectric Relaxation and Reliability of High-k MIM Capacitor Under Constant Voltage Stress

This paper investigated pixel characteristics with a split of transfer gate structure in CMOS image sensor. It is shown that the transfer gate (TG) should be as wide as possible for the given pixel structure for lag–free pixel operation. This investigation uncovered relationships between transfer gate geometry and pixel performance that could provide guidance when designing pixel structure. In particular, it shows how sensitive pixel fixed pattern noise is to the transfer gate width. Experimental results indicate that pixel fixed pattern noise can be reduced to be less than 1%.