Sun Woo Kim

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack

A perfect ohmic contact formation technique for low-resistance source/drain (S/D) contact of germanium (Ge) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. A metal-interlayer-semiconductor (M-I-S) structure with an ultrathin TiO2/GeO2 interlayer stack is introduced into the contact scheme to alleviate Fermi-level pinning (FLP), and reduce the electron Schottky barrier height (SBH). The TiO2 interlayer can alleviate FLP by preventing formation of metal-induced gap states (MIGS) with its very low tunneling resistance and series resistance and can provide very small electron energy barrier at the metal/TiO2 interface. The GeO2 layer can induce further alleviation of FLP by reducing interface state density (Dit) on Ge which is one of main causes of FLP. Moreover, the proposed TiO2/GeO2 stack can minimize interface dipole formation which induces the SBH increase. The M-I-S structure incorporating the TiO2/GeO2 interlayer stack achieves a perfect ohmic characteristic, which has proved unattainable with a single interlayer. FLP can be perfectly alleviated, and the SBH of the metal/n-Ge can be tremendously reduced. The proposed structure (Ti/TiO2/GeO2/n-Ge) exhibits 0.193 eV of effective electron SBH which achieves 0.36 eV of SBH reduction from that of the Ti/n-Ge structure. The proposed M-I-S structure can be suggested as a promising S/D contact technique for nanoscale Ge n-channel transistors to overcome the large electron SBH problem caused by severe FLP.

Non-Alloyed Ohmic Contacts on GaAs Using Metal-Interlayer-Semiconductor Structure With SF 6 Plasma Treatment

We demonstrate the effect of SF6 plasma passivation with a ZnO interlayer in a metal-interlayer-semiconductor (MIS) structure to reduce source/drain (S/D) contact resistance. The interface trap states and the metal-induced gap states causing the Fermi-level pinning problem are effectively alleviated by passivating the GaAs surface with SF6 plasma treatment and inserting a thin ZnO interlayer, respectively. Specific contact resistivity exhibits ~104 × reduction when the GaAs surface is treated with SF6 plasma, followed by ZnO interlayer deposition, compared with the Ti/n-GaAs (~2 × 1018 cm-3) S/D contact. This result proposes the promising non-alloyed S/D ohmic contact for III-V semiconductor-based transistors.

The Effect of Interfacial Dipoles on the Metal-Double Interlayers-Semiconductor Structure and Their Application in Contact Resistivity Reduction

We demonstrate the contact resistance reduction for III-V semiconductor-based electrical and optical devices using the interfacial dipole effect of ultrathin double interlayers in a metal-interlayers-semiconductor (M-I-S) structure. An M-I-S structure blocks metal-induced gap states (MIGS) to a sufficient degree to alleviate Fermi level pinning caused by MIGS, resulting in contact resistance reduction. In addition, the ZnO/TiO2 interlayers of an M-I-S structure induce an interfacial dipole effect that produces Schottky barrier height (ΦB) reduction, which reduces the specific contact resistivity (ρc) of the metal/n-type III-V semiconductor contact. As a result, the Ti/ZnO(0.5 nm)/TiO2(0.5 nm)/n-GaAs metal-double interlayers-semiconductor (M-DI-S) structure achieved a ρc of 2.51 × 10-5 Ω·cm2, which exhibited an ∼42 000× reduction and an ∼40× reduction compared to the Ti/n-GaAs metal-semiconductor (M-S) contact and the Ti/TiO2(0.5 nm)/n-GaAs M-I-S structure, respectively. The interfacial dipole at the ZnO/TiO2 interface was determined to be approximately -0.104 eV, which induced a decrease in the effective work function of Ti and, therefore, reduced ΦB. X-ray photoelectron spectroscopy analysis of the M-DI-S structure also confirmed the existence of the interfacial dipole. On the basis of these results, the M-DI-S structure offers a promising nonalloyed Ohmic contact scheme for the development of III-V semiconductor-based applications.

Effect of Metal Nitride on Contact Resistivity of Metal-Interlayer-Ge Source/Drain in Sub-10-nm n-Type Ge FinFET

A metal nitride-interlayer-semiconductor source/ drain (MN-I-S S/D) model is newly proposed to investigate the effect of tantalum nitride (TaN) on the specific contact resistivity (ρ_c) of an MN-I-S S/D with an undoped interlayer (undoped-IL) or a heavily doped IL (n⁺-IL) in sub-10-nm n-type Ge FinFETs. In this model, the workfunction variation of TaN was considered following the Rayleigh distribution. Compared with MN-I-S structures with an undoped-IL, structures with an n⁺-IL generate much lower ρ_c values (i.e., ~2 × 10^-9 Ω · cm²) and are less prone to variation. In addition, the impact of Pc variation on device performance is investigated using 3-D technology computer aided design simulation for undoped or heavily doped ILs in MN-I-S S/D structures. MN-I-S S/Ds with an n⁺-IL can achieve much lower current variation and a higher ON-state drive current.

Analytical study of polymer deposition distribution for two-dimensional trench sidewall in low-k fluorocarbon plasma etching process

In this study, a new polymer deposition distribution model for a two-dimensional low-k porous SiOCH trench structure during the fluorocarbon plasma etching process is described so as to investigate the bowing effect in a nanoscale trench. The model consists of three processes, namely, (1) polymer reflection, (2) ion-assisted polymer deposition, and (3) ion-assisted polymer emission. To calculate the distribution of the polymer, the polymer flux arrived at the surface points of the trench was calculated based on the model. To estimate the profile of the trench, the flux of the etchants at the point of the trench surface was also considered. The simulated etching process is based on a simple flux model, which takes into account angular distributions for ions and radicals from the sheath edge to the trench. Simulation results show that the lower section of the sidewall had a larger number of polymer particles than the other positions of the sidewall did. According to the simulated results, the sidewall bowin...