Sundar G. Sankaran

An Integrated Draft 802.11n Compliant MIMO Baseband and MAC Processor

A 3 times 3 MIMO baseband and MAC processor in 0.18 mum 6M CMOS occupies 62.1 mm2 and dissipates (Tx/Rx) 1379/1200mW at 1.8V including ADCs, DACs, and PCI/PCIe PHY. The integrated BB and MAC delivers up to 300Mb/s in 40MHz bandwidth, greater than 150Mb/s TCP throughput best case and a maximum range of 700ft range.

Design and implementation of a CMO 802.11n SoC

Wireless local area networks based on the IEEE 802.11 standard are rapidly replacing wires within homes and offices. The latest data-rate amendment to the IEEE 802.11 standard, known as the 802.11n, provides enhanced user experience by exploiting MIMO techniques that use multiple antennas for both transmitter and receiver. In conjunction with MAC layer improvements such as aggregating data, the 802.11n standard supports PHY data rates as high as 600 Mb/s with four spatial streams. This article discusses various MAC and PHY level modifications introduced in 802.11n, as well as the architecture, design trade-offs, and implementation details of a two spatial stream CMOS 802.11n-draft-compliant SoC.