Sunfei Fang

High performance and low power transistors integrated in 65nm bulk CMOS technology

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

Dual workfunction fully silicided metal gates

Fully silicided (FUSI), dual workfunction (WF), Ni monosilicide metal gates are demonstrated using Sb predoped polySi for setting the nFET WF and for the first time a combination of Al predoped polySi and a Ni(Pt) alloy silicide for the pFET WF. The combination of the Sb and Al predoped polySi along with the Ni(Pt)Si, allow for WFs spanning the Si band gap to within 0.2 eV of the band edges. With this large WF range the FUSI, dual WF, NiSi process is applicable for both high performance and low power CMOS applications. It is shown that the Al and Sb predoped polySi and the Ni(Pt)Si alloy have leakage currents equivalent to NiSi formed from intrinsic polySi. A fundamental voiding problem in the formation of CoSi/sub 2/ metal gates is also demonstrated, indicating the superiority of the NiSi gates.

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved with SPT. Leading edge PFET Ion=660muA/mum at Ioff=100nA/mum at 1V Vdd operation is demonstrated without using embedded SiGe junctions. Inverter ring oscillator delay is reduced by 15% with SPT

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.

A 0.039um 2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

We present industrys smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovation of High-K Metal (HK/M) stack in the Deep Trench (DT) capacitor. This has enabled 25% higher capacitance and 70% lower resistance compared to conventional SiON/Poly stack at matched leakage and reliability. The HKMG access transistor developed in high performance optimized technology features sub 3fA leakage and well-controlled threshold voltage sigma of 40mV. The fully integrated 32Mb product prototypes demonstrate state of the art performance with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.

Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances

Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overlap capacitance and the capacitance between the gate stack and metal contacts. These results are consistent with modeling. Although this is demonstrated with 65 nm devices, low-k spacers can cut active power consumption and have the potential to improve performance through reductions in parasitic capacitances which will be of greater importance for future technology nodes.

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well

A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate

This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.

Characterization of novel TiN/HfO 2 metal insulator semiconductor stack for 32nm eDRAM

In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has successfully integrated high-к and metal films as part of the trench capacitor. In addition, these films are found to be fully compatible with front-end of line (FEOL) thermal budgets. We explore sources of variation and illustrate process mitigation techniques, including the targeting of key capacitor properties, and reduction in trench leakage. Finally, we illustrate that systematic and random variations do not pose as insurmountable barriers, and that the trench technology is scalable to the 22nm trench and beyond.

Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond

A novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520 uA/um at Ioff of InA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.