Thomas W. Dyer

Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy

Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE) technique for the first time. The very simple process uses no recess etch or epi deposition steps, adds minimal process cost, and can be easily integrated into a standard CMOS process. With a record high 1.65 at% substitutional C concentration in source and drain, 615 MPa uniaxial tensile stress was introduced in the channel, leading to a 35% improvement in electron mobility and 6% and 15% current drive increase in sub-40 and 200 nm channel length devices respectively.

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved with SPT. Leading edge PFET Ion=660muA/mum at Ioff=100nA/mum at 1V Vdd operation is demonstrated without using embedded SiGe junctions. Inverter ring oscillator delay is reduced by 15% with SPT

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 muA/mum have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/mum. Junction profiles have been optimized to reduce the gate-induced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well