Paul E. Nicollian

Material dependence of hydrogen diffusion: implications for NBTI degradation

Negative bias temperature instability (NBTI) is known to exhibit significant recovery upon removal of the gate voltage. The process dependence of this recovery behavior is studied by using the time slope (n) as the monitor. We observe a systematic variation of n with oxide thickness, nitrogen concentration, and fluorine implantation. Incorporation of the material dependence of the diffusivity within the reaction-diffusion (R-D) framework captures the observed trends. The consequences of this modification are (a) diffusion limitation is shown to arise from diffusion in poly-Si, rather than oxide, (b) a plausible explanation for low-voltage stress induced leakage current (LV-SILC) naturally appears. Important findings are (a) NBTI degradation remains significant at high frequencies, (b) numerical simulations at moderate frequencies can be used to predict circuit impact in the GHz regime, (c) high frequency operation can be modeled as a lower effective DC stress

Experimental evidence for voltage driven breakdown models in ultrathin gate oxides

We have performed an experiment proving that the widely accepted E-field TDDB model is a physically incorrect description of breakdown in ultrathin gate oxides. Although interface traps are the dominant SILC mechanism below 5 V stress, breakdown remains limited by bulk trap generation and is voltage-driven. It has been recently proposed that the anode hole injection model is still operative at low voltages. Although we will show that holes do generate bulk traps and cause breakdown in ultrathin oxides, hole injection does not completely account for all of the trap generation mechanisms observed during direct tunneling stress.

Negative bias temperature instability mechanism: The role of molecular hydrogen

The role of dimerization of atomic hydrogen to give molecular hydrogen in determining negative bias temperature instability (NBTI) kinetics is explored analytically. The time dependency of NBTI involving molecular hydrogen was found to obey a power law with a slope of 1∕6, as opposed to the 1∕4 slope derived for a reaction involving atomic hydrogen. The implications of this dimerization reaction for voltage and temperature acceleration are also discussed. Simulation results validating these predictions are also described. The higher slopes typically reported for NBTI are shown to be an artifact of measurement, and experimental data supporting this lower time dependency is shown.

Low voltage stress-induced-leakage-current in ultrathin gate oxides

Stress-induced-leakage-current (SILC) is an important concern in ultrathin gate oxides because it may impose constraints on dielectric thickness scaling. We show that for oxides less than /spl sim/3.5 nm thick, interfacial traps generated from direct tunneling stress result in a sense voltage dependent SILC mechanism that can dominate the gate leakage current at low operating voltages.

Trends for deep submicron VLSI and their implications for reliability

We examine the technology trends in both device and interconnect process integration flow design, in order to put into perspective the corresponding implications on reliability activities. We illustrate trends in several major reliability areas: reduced failure rate requirements; vanishing of excess reliability margins; sensitivity of reliability mechanisms integration flow design and scaling; increased use of simulation to estimate reliability; and examining mechanisms for new regimes of operation. Next we assess the strengths and weaknesses of current build-in reliability activities. This process identifies several key areas where improved knowledge and capability are needed in the overall build-in reliability process: improve the circuit modeling of wearout phenomena; develop new gate dielectrics to increase performance while maintaining reliability; determine if there is a discontinuity caused by entering the direct tunneling regime of gate oxide operation; increase understanding of thermal limitations on interconnect design guidelines in multilevel metal systems; and enhance emerging methodologies for ESD/EOS build-in reliability.

Ultrathin nitrogen-profile engineered gate dielectric films

A simple and novel scheme is presented for the formation of /spl sim/4 nm gate dielectric films with nitrogen at the top (gate electrode/dielectric) interface. It consists of low-temperature, remote, high-density N/sub 2/-plasma nitridation of thermal SiO/sub 2/, followed by a post-nitridation anneal. The key results are: (a) high N concentrations (10-20 at.%) incorporated uniformly within /spl sim/0.7 nm of the oxide surface, (b) little V/sub fb/-shift and no significant variation in midgap-D/sub it/ from that of control oxide, (c) suppression of B-penetration for high B levels and for high thermal budgets including a hydrogen ambient, and (d) no evidence of damage to the oxide.

Extending the reliability scaling limit of SiO/sub 2/ through plasma nitridation

We demonstrate a manufacturable remote plasma nitridation process that significantly extends the reliability scaling limit of SiO/sub 2/ based gate dielectrics.

Analytic Extension of the Cell-Based Oxide Breakdown Model to Full Percolation and its Implications

We extend the cell-based approach of Sune to full percolation that is predictive down to 0.4nm. We resolve conflicting reports in the literature on the scaling behavior of the Weibull shape parameter with oxide thickness, and show that Weibull statistics can be violated if pre-existing traps are present.

Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics

Electrical instability due to charge trapping in high-k materials is a primary concern for the usefulness of these films in future CMOS devices. This paper reports the effect of charge trapping on the threshold voltage and transistor drive current of devices made with HfSiON gate dielectric. Our results show that the physics of the charge trapping in HfSiON is unique and follows logarithmic dependence with time rather than usual exponential dependence. NMOS devices fabricated with HfSiON films show acceptable electrical stability for 10 years without substantial degradation of either the threshold voltage or the drive current.

The Traps that cause Breakdown in Deeply Scaled SiON Dielectrics

The paper shows that a minimum of two traps is required to cause breakdown in SiON films down to 10A. At least one trap must be an interface state and at least one must be a bulk state. At low voltages, the rate limiting step for breakdown is the generation of interface traps and is controlled by the release of H0