Jerry C. Hu

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.

Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100 nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced by the metal gate. This allows the temperatures after metal gate definition to be limited to 450/spl deg/C. Compared to pure SiO/sub 2/, the nitrided oxides provide increased capacitance with less penalty in increased gate current. A saturation transconductance (g/sub m/) of 1000 mS/mm is obtained for L/sub gate/=70 nm and t/sub OX/=1.5 nm. Peak cutoff frequency (f/sub T/) of 120 GHz and a low minimum noise figure (NF/sub min/) of 0.5 dB with associated gain of 19 dB are obtained for t/sub OX/=2 nm and L/sub gate/=80 nm.

Physical oxide thickness extraction and verification using quantum mechanical simulation

Physical gate oxide thickness is extracted from TiN gate PMOS and NMOS capacitance voltage measurements using an efficient multi-band Hartree self-consistent Poisson solver. The extracted oxide thicknesses are then used to perform direct tunneling current simulations. Excellent agreement between measured a simulated tunnel current is obtained without the use of adjustable fitting parameters.

Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (/spl les/33 /spl Aring/) and with high temperature (>950/spl deg/C) S/D annealing for 0.13 /spl mu/m CMOS applications. Close to ideal C-V characteristics are obtained indicating good Si/SiO/sub 2/ interface quality and free from gate depletion. The gate sheet resistance is about 2 ohm//spl square/, nearly constant down to 0.05 /spl mu/m. Under fixed effective fields, the electron and hole mobility are comparable to or slightly better than those of poly gate devices. Compared to poly gate devices, the W/TiN on 33 /spl Aring/ pure oxide has inferior charge-to-breakdown (Q/sub bd/) distribution under substrate (+V/sub G/) injection. However, a remote-plasma nitrided oxide (RPNO) can greatly improve the +V/sub G/ Q/sub bd/ distribution for the W/TiN case. Short-channel W/TiN pMOS transistors are fabricated with excellent characteristics down to L/sub gate//spl ap/0.07 /spl mu/m. For nMOS under +V/sub G/ direct tunneling (DT) or Fowler-Nordheim (F-N) tunneling injection with S/D grounded, the W/TiN device has a higher substrate hole current density (J/sub p/) than n/sup +/ poly-gate device (by about an order magnitude larger). This higher J/sub p/ is believed due to the tunneling of valence-band electron and thus has no impact on the thin (t/sub ox//spl les/33 /spl Aring/) gate oxide reliability.

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

High performance 0.1 /spl mu/m (physical) gate length CMOS with 30 /spl Aring/ gate dielectric (C-V: gate accumulated at V/sub gb/=-3 V) is demonstrated at 1.0 V-1.5 V. Scaling to 0.1 /spl mu/m L/sub gate/ CMOS is described. At 1.5 V, nMOS strong and nominal I/sub drive/=757 and 700 /spl mu/A//spl mu/m, and pMOS strong and nominal I/sub drive/=337 and 300 /spl mu/A//spl mu/m. For high performance at 1.0 V, n- and pMOS are designed with low V/sub T/ and higher I/sub off/ (100 nA//spl mu/m at L/sub g//sup min/). At 1 V, nMOS strong and nominal I/sub drive/ is 516 and 473 /spl mu/A//spl mu/m; pMOS strong and nominal I/sub drive/ is 220 and 188 /spl mu/A//spl mu/m. Benchmarking to FOM and CV/I metrics is performed for this 1.0-1.5 V, 0.1 /spl mu/m node and prior 1.8-1.5 V, 0.18 /spl mu/m nodes. Present 1.5 V, 0.1 /spl mu/m CMOS (as well as our recently reported 1.8-1.5 V, 0.18 /spl mu/m CMOS) has FOM and CV/I values better than the literature trend. The FOM at V/sub DD/=1.0 V (max I/sub off/=100 nA//spl mu/m) is the same as the 1.5 V FOM (max I/sub off/=1 nA//spl mu/m).

A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

CVD W/CVD TiN stacks are studied for the first time as gate electrodes on 3 nm gate oxide and compared with the CVD W/PVD (sputtering) TiN gate stacks and the baseline n/sup +/ poly gate. It is found that the PVD TiN has higher metal-to-SiO/sub 2/ barrier height (/spl sim/3.77 eV) than that of the CVD TiN (3.62 eV). The CVD W/PVD TiN gates without high temperature (>900 C) RTP anneal show good electrical characteristics on 3 nm gate oxide, and the CVD TiN is less favorable due to its high impurities. High temperature anneal cause fluorine in CVD W to diffuse and interact with the gate oxide which adversely affect the gate oxide integrity (GOI). The remote plasma nitrided gate oxide (RPNO) provides a barrier between the TiN and gate oxide, and thus prevents or reduces the F-SiO/sub 2/ interaction, resulting in metal gate GOI comparable to that of poly gate. The CVD metal gate is a good candidate for the non-conventional, high aspect ratio grooved gate structures due to its good conformality.

A 1.2V, sub-0.09 /spl mu/m gate length CMOS technology

CMOS technology for 1.2 V high performance applications is being scaled to sub-0.09 /spl mu/m physical nominal gate lengths and with effective gate dielectric thickness less than 2 nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09 /spl mu/m (post gate reoxidation), and gate dielectric thickness of 2.7 nm (nMOS), 3.0 nm (pMOS) (inversion at 1.2 V), nMOS and pMOS I/sub drive/ is 763 /spl mu/A//spl mu/m and 333 /spl mu/A//spl mu/m respectively, at 1.2 V with maximum I/sub off/=5 nA//spl mu/m. Gate-drain overlap in this work is /spl sim/210 /spl Aring//side and bottomwall junction capacitance is reduced to 0.8 fF//spl mu/m/sup 2/ (pMOS) and 1.1 fF//spl mu/m/sup 2/ (nMOS). With reduced parasitics and high drive current, the 1.2 V technology FOM (Figure-of-Merit) is >39 GHz, meeting the roadmap trend.

A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)

A high performance 1.5 V, sub-0.18 /spl mu/m (physical) gate length CMOS technology and extension to a 1.0 V technology for low power applications is described. nMOS with nominal I/sub drive/=740, 580, and 380 /spl mu/m are achieved for V/sub DD/=1.8, 1.5, and 1.0 V at accumulation t/sub ox/=36 A (from C-V at V/sub gb/=-3 V). pMOS with nominal I/sub drive/ of 300 (1.8 V), 222 (1.5 V), and 140 /spl mu/A//spl mu/m (1.0 V) are achieved. Target L/sub g//sup min/ (minimum gate length)=0.15-0.16 /spl mu/m. Drive currents are comparable to a recently reported 0.08 /spl mu/m CMOS process. Low nMOS R/sub SD/<220 /spl Omega/-/spl mu/m and pMOS R/sub SD/<500 /spl Omega/-/spl mu/m are achieved. Improvements to 1.5 V CMOS include CoSi/sub 2/ cladding, pocket implant for n- and pMOS, increased HDD and S/D dose with increased anneal, and low temperature backend processing <700/spl deg/C. Scaling of the 1.5 V CMOS to 1.0 V CMOS is achieved by (a) reduction of V/sub T/ implant dose or (b) use of shallow channel counterdoping (CD) if the V/sub T/ dose cannot be reduced further. With reduced V/sub T/ dose, nominal V/sub T//sup sat/ is reduced from 0.25 V (1.5 V CMOS) to 0.10 V (1.0 V CMOS) with small short-channel effect (SCE) for both designs. With CD and same pocket process from 1.5 V CMOS, low V/sub T/ devices are achieved with lower and constant V/sub t//sup sat/=0.06 V from L/sub gate/=0.25-0.25 /spl mu/m and with low SCE. Inverter chain delay of 37 psec for the 1.0 V, 36 A, 0.18 /spl mu/m CMOS is reduced 40% compared to a prior 1.0 V, 48 A, 0.25 /spl mu/m process.

Feasibility study to determine the suitability of using TiN/W and Si1-xGex as alternative gate materials for sub-0.1-μm gate-length PMOS devices

In this paper we report on a simulation study on the impact of gate material on PMOS device performance. The gate materials studied were conventional poly-silicon gate, SiGe gate with varying Ge composition,and TiN/W metal gate. The motivation for alternative gate materials is to progressively alleviate or eliminate the poly depletion problem as observed with existing poly-silicon gate material, which becomes increasingly more important as the gate oxide becomes ultra thin (less than or equal to 26 Angstrom). Using these alternative gate materials, drive currents can be higher than those with conventional poly-silicon gate material, especially for PMOS devices where gate depletion is more pronounced. Two types of PMOS device designs were studied: (1) a high- performance design which is characterized by a maximum off current of 1nA/micrometer, and (2) a low-power design characterized by a maximum off current of 10 pA/micrometer. A plus or minus 10% variation in gate length is allowed for the high-performance design, and a larger variation for the low- power design. The minimum allowed gate length is 0.09 micrometer in both cases. Key results obtained from this study are as follows. First, use of TiN gate material results in a 30% improvement in pMOS nominal drive current compared to conventional poly-Si gate pMOS devices for the low-power device design, and a 15% pMOS nominal drive current improvement for the high-performance device design. Second, use of SiGe gate material results in a 25% improvement in nominal pMOS drive current compared to conventional poly-Si gate pMOS for the low-power device design, and a 13% pMOS nominal drive current improvement for the high-performance device design.

Shallow p-type source/drain extension formation using B2H6 plasma doping for deep submicron CMOS

In this paper, we studied the feasibility of using a commercial etch chamber to perform plasma doping to form shallow p+-n junction. The plasma doping has the advantage of high wafer throughput compared to conventional low energy implanters. Ultra-shallow boron implantation was done in a plasma reactor with a Helicon plasma source and a gas mixture of He+B2H6. 0.18 micrometer class PMOS devices were fabricated using the plasma doping and compared with devices with a conventional BF2 S/D extension implant (10 keV BF2 implant, Xj approximately equals 650 Angstrom). The key results are as follows. (1) Shallow boron implant with good process uniformity on a wafer was achieved using the plasma doping process. Boron dose of approximately 5E14 cm-2 and junction depth (Xj) of approximately 250 Angstrom was achieved after S/D annealing. (2) The pMOS devices fabricated using the plasma doping have much better short channel effect (SCE) characteristics than the devices fabricated with 10 keV BF2 implant. The improvement of Xj in the vertical direction of a transistor (from approximately 650 angstrom to approximately 220 angstrom) using the plasma doping resulted in an improvement of approximately 450 angstrom in the lateral direction shown in Lgmin. (3) Degradation in gate-depletion was observed for the plasma doping devices; however, the degradation can be recovered by using an extra gate implant step. (4) Compared to devices with the conventional implant, higher Rsd was found in devices with the plasma doping process. This higher Rsd for the B2H6 cases was most likely due to the less gate-to-drain overlap and carbon/oxygen contaminants introduced during the plasma doping process. (5) Higher gate- edge diode leakage was also observed in the plasma doping devices. The high diode leakage was believed also due to the contaminants.