Suock Chung

Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

A compact STT(Spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30nm can be smaller than 8F2.

Ultrathin (l10nm) Nb 2 O 5 /NbO 2 hybrid memory with both memory and selector characteristics for high density 3D vertically stackable RRAM applications

We report, for the first time, the novel concept of ultrathin (~10nm) W/NbO_x/Pt device with both threshold switching (TS) and memory switching (MS) characteristics. Excellent TS characteristics of NbO₂, such as high temperature stability (~160°C), fast switching speed (~22ns), good switching uniformity, and extreme scalability of device area (φ~10nm)/thickness (~10nm) were obtained. By oxidizing NbO₂, we can form ultrathin Nb₂O₅/NbO₂ stack layer for hybrid memory devices with both TS and MS. Without additional selector device, 1Kb cross-point hybrid memory device without SET/RESET disturbance up to 10⁶ cycles was demonstrated.

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

Thickness effect of ultra-thin Ta2O5 resistance switching layer in 28 nm-diameter memory cell

Resistance switching (RS) devices with ultra-thin Ta2O5 switching layer (0.5–2.0 nm) with a cell diameter of 28 nm were fabricated. The performance of the devices was tested by voltage-driven current—voltage (I-V) sweep and closed-loop pulse switching (CLPS) tests. A Ta layer was placed beneath the Ta2O5 switching layer to act as an oxygen vacancy reservoir. The device with the smallest Ta2O5 thickness (0.5 nm) showed normal switching properties with gradual change in resistance in I-V sweep or CLPS and high reliability. By contrast, other devices with higher Ta2O5 thickness (1.0–2.0 nm) showed abrupt switching with several abnormal behaviours, degraded resistance distribution, especially in high resistance state, and much lower reliability performance. A single conical or hour-glass shaped double conical conducting filament shape was conceived to explain these behavioural differences that depended on the Ta2O5 switching layer thickness. Loss of oxygen via lateral diffusion to the encapsulating Si3N4/SiO2 layer was suggested as the main degradation mechanism for reliability, and a method to improve reliability was also proposed.

Effect of oxygen migration and interface engineering on resistance switching behavior of reactive metal/polycrystalline Pr 0.7 Ca 0.3 MnO 3 device for nonvolatile memory applications

An in-depth study on the resistive switching mechanism of perovskite oxide based device was performed. Compared with filament type resistive switching device, excellent switching uniformity was obtained due to controlled redox reaction at metal/oxide interface. Electromigration of oxygen ion under the bipolar electric filed can explain the switching behavior. Formation of ultrathin AlOx at the interface can guarantee excellent retention characteristics at 125 °C. Compared with the large area (50 × 50 um2) memory cell, the nanoscale device (Φ=50 nm) showed better memory performance such as faster switching speed, better uniformity, endurance, and retention characteristics.

NbO 2 -based low power and cost effective 1S1R switching for high density cross point ReRAM Application

In this paper, 5Xnm cross point cell array for the low power ReRAM operation was developed with 1S1R cell structure. Through the optimization of both TiOx/TaOx based-1R and NbO2 based-1S stacks with TiN based-electrode, the worlds first and best bipolar switching characteristics with the lowest operation current (20~50uA) and sneak current (~1uA) level were acquired.

Varistor-type bidirectional switch (J MAX >10 7 A/cm 2 , selectivity∼10 4 ) for 3D bipolar resistive memory arrays

We demonstrate a varistor-type bidirectional switch (VBS) with excellent selection property for future 3D bipolar resistive memory array. A highly non-linear VBS showed superior performances including high current density (>;3×10⁷A/cm²) and high selectivity (~10⁴). The non-linear I-V characteristics can be explained by varistor-type multi-layer tunnel barriers, which were formed by Ta incorporation into thin TiO₂. Furthermore, the 1S1R device showed excellent suppression of leakage current (>;10⁴ reduction) at 1/2V_READ, which is promising for ultra-high density resistive memory applications.

Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM

In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was characterized with the integration of selector and resistor materials.

Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurement, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO/sub 2//nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.

A novel method for forming gate spacer and its effects on the W/WN/sub x//poly-Si gate stack

A novel method for forming the SiO/sub 2//Si/sub 3/N/sub 4/ (O/N) gate spacer has been developed through applying a low temperature atomic layer deposition (ALD) SiO/sub 2/ film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate birds beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at the same V/sub t/, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.