Susan H. Downey

3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments

This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in the copper/low-k stack are evaluated. The modeling strategy also includes an in-house developed energy based analysis. For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, several bond pad architectures have been implemented and wire bonded on a test vehicle. It was found a significant effect of the copper/low-k design on peeling failure rates, in particular with severe bonding conditions. In this paper, typical modeling results are presented. Contrary to stress based one, the energy based analysis shows a better ability to forecast the observed failed interface. From simulation results obtained, it is confirmed that the bonding process plays major role in the peeling failure, despite the fact that most of them are observed during the wire pull test. Failure mechanisms are also proposed. Then, the implemented pad structures are evaluated and analyzed. Both general trends and architecture ranking are provided. Simulations are then faced to experimental results and a full agreement is found. The complementary nature of the energy based failure criteria is again highlighted through a clearer discrimination of the tested structures. Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.

Gold Wire Bonding Induced Peeling in Cu/Low-k Interconnects: 3D Simulation and Correlations

Amongst solutions to connect the die to the package, thermosonic wire bonding process remains widely used. However, the introduction of low-k dielectric materials, and the feature size decrease of IC chips to follow Moores law, pose great integration challenge. This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in both the gold wire and the copper/low-k stack have been evaluated and discussed. The modeling strategy also includes an in-house developed energy based analysis. For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, the effect of the bonding conditions has been studied. More precisely, it was found that the peeling failure rates are significantly dependant on the used wire types and their respective bonding parameters. In this paper, some numerical parameters are firstly discussed and the most suitable modeling strategy is proposed. Hence, typical results are presented, and the comparison of the peeling hazard induced by distinct bonding conditions is carried out. Simulations are then faced to experimental results and a good agreement is found. In addition to that, the complementary nature of the energy based failure criteria is highlighted through a clearer determination of the forecasted location of the failed interface in the IC stack. Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.