T. Iizuka

Hot-carrier generation in submicrometer VLSI environment

Submicrometer MOSFETs may suffer from reliability degradation, which has a strong correlation with substrate current. In order to know what is happening to substrate current in a VLSI environment, a substrate-current circuit simulator is developed. The simulator is applied to MOS unit circuit blocks, VLSI static memories, and dynamic memories, and their hot-carrier duty ratios are calculated. A new circuit technology, called normally-on enhancement MOSFET insertion (NOEMI), is proposed which can suppress hot-carrier generation. Several design implications for submicrometer VLSIs are obtained through the analysis.

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

Gate electrode RC delay effects in VLSI's

A poly-silicon gate electrode can be considered as a distributed RC line. The delay induced by this RC time constant can become a limitation in designing high-speed VLSIs. This effect, called the gate electrode RC delay effect (GERDE), is studied for short-channel MOSFETs. A simple formula is derived to roughly estimate the GERDE, which can be used as a rule-of-thumb in VLSI design. An approximation of the GERDE by a simple lumped-circuit model is also described. The future trends of the GERDE are investigated and it is concluded that the GERDE gets more severe for shorter channel MOSFETs, but, if the gate width is confined up to 30 µm, the GERDE can be neglected for MOSFETs with a channel length of more than 0.8 µm. For a large conductance, division of the MOSFET width is shown to be effective through experiments.

A 1Mb virtually SRAM

Suppressed VLSI with Submicron Geometry”, ISSCC DIGEST ’Sakurai, T., Kakumu, M . and Iizuka, T., “Hot-Carrier O F T E C H N I C A L P A P E R S , p. 272-273; Feb., 1985. “HotJ S S C ; to he published. Carrier Generation in Submicron VLSI Environment”, IEEE Insertion (NOEMI) technology5 is applied selectively to bootstraped nodes to endow hot-carrier resistancy to the circuits. N-channel memory cells are embedded in a P-well for protection from the minority carrier injection from I/O pins and alpha-particle induced electrons. Yo substrate bias is applied to reduce the standby current. Process related parameters are listed in Table 1. A double-level poly-Si and double level A1 process has been employed for circuit speed. The cell capacitor is planar and the design rule is 1.2pm. A microphotograph of the chip is shown in Figure 4. Figure 5 demonstrates a typical address access time of 62ns. The slower access is the worst case access time; Le., refresh operation taking place in advance of the normal access. The faster access is without refresh. This measurement is carried out by a test enable pin that affords control of the refresh-request signal externally. Since the access time without refresh is 48ns, the access time overhead by the background refresh is 29%. Electron beam tested internal waveforms are also shown in Figure 5. Quick switch from refresh to normal operation can be achieved by the dual bootstrap system, where one system is precharged when the other one is in operation. The pin configuration is shown in Figure 6. SRAMs. The SRAM is believed to be a promising substitute for large-capacity Acknowledgments The authors wish to thank S. Fujii, S. Saito, K. Natori, T. Ohtani, K. Taniguchi, Y. Nishi and K. Shimuzu for encouragement and discussions. Theyalso thank Y. Ito, K. Sat0 and K. Matsuda for support. Technology Twin well CMOS Layers Double poly-Si and double A1 Gate length l .op(NMOS), 1.2puPMOS) Junction depth 0.20,u(N+), 0.35p(Pt) Cap. oxide thickness l0nm Gate oxide thickn ss 20nm Poly-Si (WidthlSpace) 1.0pm / 1.4pm 1 s t AI (WidthlSpace) 1.3pm / 1.5pm Contact hole 1.lpm / 1.4pm 2nd Al (WidthlSpace) 1.8pm / 1.9pm Via hole 1.8pm / 2.0pm TABLE 1-Process parameters.

A 46ns 256K CMOS SRAM

A 46ns 32K×8 CMOS RAM fabricated with double metal, double poly 1.2μm P-well technology will be reported. The RAM(59.2mm²) has a 10mW operating power at 1MHz and a 30μW standby power.