Tokumasa Yasui
Hitachi
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Tokumasa Yasui.
international solid-state circuits conference | 1982
Osamu Minato; T. Masuhara; T. Sasaki; Yoshio Sakai; Tetsuya Hayashida; Kouichi Nagasawa; K. Nishimura; Tokumasa Yasui; T. Miyauchi
A fully-static 8K×8b RAM using HICMOSII technology with a typical address access time of 65ns and power dissipation of 200mW will be discussed. To improve manufacturing yield a laser redundancy technique utilizing a N+ -i-N+ polysilicon structure was employed.
IEEE Transactions on Electron Devices | 1985
Yuji Yatsuda; Shinji Nabetani; Ken Uchida; Shinichi Minami; Masaaki Terasawa; Takaaki Hagiwara; H. Katto; Tokumasa Yasui
Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 104write/erase cycles.
international solid-state circuits conference | 1985
Sho Yamamoto; Kiyofumi Uchibori; Kouichi Nagasawa; Satoshi Meguro; Tokumasa Yasui; Osamu Minato; T. Masuhara
A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm2memory cell.
international solid-state circuits conference | 1980
T. Masuhara; Osamu Minato; T. Sasaki; H. Nakamura; Yoshio Sakai; Tokumasa Yasui; Kiyofumi Uchibori
A pair of HCMOS static RAMs with 2K word×8b organization, using JFET-powered static RAM cells and operating at 74ns typical access time, operating power of 200mW and standby power of 25μW will be described.
Archive | 1982
Nobuyoshi Tanimura; Tokumasa Yasui
international solid-state circuits conference | 1978
T. Masuhara; Osamu Minato; T. Sasaki; Yoshio Sakai; Masaharu Kubo; Tokumasa Yasui
Archive | 1978
Tokumasa Yasui; Minoru Fukuda; Tatsumi Shirasu
Archive | 1979
Nobuyoshi Tanimura; Hiroshi Fukuta; Kotaro Nishimura; Tokumasa Yasui
Archive | 1976
Tokumasa Yasui
Archive | 1977
Tokumasa Yasui; Shinji Shimizu; Kotaro Nishimura