T. Y. Liow

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Silicon-based horizontal nanoplasmonic slot waveguides for on-chip integration

Horizontal metal/insulator/Si/insulator/metal nanoplasmonic slot waveguide (PWG), which is inserted in a conventional Si wire waveguide, is fabricated using the standard Si-CMOS technology. A thin insulator between the metal and the Si core plays a key role: it not only increases the propagation distance as the theoretical prediction, but also prevents metal diffusion and/or metal-Si reaction. Cu-PWGs with the Si core width of ~134-21 nm and ~12-nm-thick SiO2 on each side exhibit a relatively low propagation loss of ~0.37-0.63 dB/µm around the telecommunication wavelength of 1550 nm, which is ~2.6 times smaller than the Al-counterparts. A simple tapered coupler can provide an effective coupling between the PWG and the conventional Si wire waveguide. The coupling efficiency as high as ~0.1-0.4 dB per facet is measured. The PWG allows a sharp bending. The pure bending loss of a Cu-PWG direct 90° bend is measured to be ~0.6-1.0 dB. These results indicate the potential for seamless integration of various functional nanoplasmonic devices in existing Si electronic photonic integrated circuits (Si-EPICs).

Fully complementary metal-oxide-semiconductor compatible nanoplasmonic slot waveguides for silicon electronic photonic integrated circuits

Horizontal Al/SiO2/Si/SiO2/Al nanoplasmonic slot waveguides with the SiO2 width at each side of ∼15 nm and the Si core width of ∼136–43 nm were fabricated using a fully silicon complementary metal-oxide-semiconductor compatible technology. The propagation losses were measured to be ∼1.07–1.63 dB/μm at the telecommunication wavelength of 1550 nm, in agreement with those predicted from numerical simulation. A simple tapered coupler with length of ∼0.3–1 μm provides a high coupling efficiency of ∼−0.6–−1.5 dB between the plasmonic waveguide and the conventional Si dielectric waveguide. The plasmonic slot waveguide can achieve a low-loss ultracompact bend. A direct 90° bend was demonstrated to have the pure bending loss as low as ∼0.2–0.4 dB. The losses of propagation, coupling, and bending depend weakly on wavelength in the c-band. These results demonstrate the potential for seamless integration of functional plasmonic devices in existing silicon electronic photonic integrated circuits.

Fast and low power Michelson interferometer thermo-optical switch on SOI

We designed and fabricated silicon-on-insulator based Michelson interferometer (MI) thermo-optical switches with deep etched trenches for heat-isolation. Switch power was reduced approximately 20% for the switch with deep etched trenches, and the MI saved approximately 50% power than that of the Mach-Zehnder interferometer. 10.6 mW switch power, approximately 42 micros switch time for the MI with deep trenches, 13.14 mW switch power and approximately 34 micros switch time for the MI without deep trenches were achieved.

Low-loss silicon slot waveguides and couplers fabricated with optical lithography and atomic layer deposition

We demonstrate low-loss silicon slot waveguides patterned with 248 nm deep-UV lithography and filled with atomic layer deposited aluminum oxide. Propagation losses less than 5 dB/cm are achieved with the waveguides. The devices are fabricated using low-temperature CMOS compatible processes. We also demonstrate simple, compact and efficient strip-to-slot waveguide couplers. With a coupler as short as 10 µm, coupling loss is less than 0.15 dB. The low-index and low-nonlinearity filling material allows nonlinearities nearly two orders of magnitude smaller than in silicon waveguides. Therefore, these waveguides are a good candidate for linear photonic devices on the silicon platform, and for distortion-free signal transmission channels between different parts of a silicon all-optical chip. The low-nonlinearity slot waveguides and robust couplers also facilitate a 50-fold local change of the waveguide nonlinearity within the chip by a simple mask design.

Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φ m and V T tune-ability

A simple and cost-effective single metal gate scheme was successfully demonstrated to form gate-all-around (GAA) nanowire FETs with optimized dual V_T for low power CMOS applications. FUSI gate-induced stress effects were shown to be of great relevance to device performance. At an I_Off of 20 pA/mum, superior I_On of 1180 and 405 muA/mum were obtained for NFETs and PFETs at a V_DD of 1.2 V.

Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs

A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated

Thermo-Optical Enhanced Silicon Wire Interleavers

Ring-resonator (RR) and ring-assisted (RA) Mach-Zehnder interferometer (MZI) interleaver structures with thermo-optical fine tuning are proposed and fabricated on silicon-on-insulator. With thermo-optical fine tuning, the crosstalks are improved from ~12 to ~22 dB and from ~6 to ~17 dB for RR- and RA-MZI interleavers, respectively. In a wavelength range of 40 nm, the RR-MZI interleaver structure has more uniform responses whereas the RA-MZI interleaver structure has sharper rolloffs.

Omega-Gate p-MOSFET With Nanowirelike SiGe/Si Core/Shell Channel

We demonstrated, for the first time, p-MOSFETs (LG ges 40 nm) with SiGe/Si core/shell channel integrated on bulk Si using a CMOS-compatible top-down processes. The Omega-shaped nanowire (NW)-like channels comprised of ~12-nm-thick inner SiGe core and 4-nm-thick outer Si shell. The devices exhibited good subthreshold characteristics (with SS ~128 mV/dec), suggesting successful surface passivation of the SiGe NW body by the outer Si capping layer. Drive currents of ~167 muA/mum is achieved, which is 15% enhancement over the reference Si-channel devices fabricated by the same process. Double gm peaks are observed at low drain bias for the core/shell SiGe NW devices, confirming the quantum confinement of holes in the SiGe inner core.

Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique

A top-down approach of forming SiGe-nanowire (SGNW) MOSFET, with Ge concentration modulated along the source/drain (Si_0.7Ge_0.3) to channel (Si_0.3Ge_0.7) regions, is presented. Fabricated by utilizing a pattern-size-dependent Ge-condensation technique, the SGNW heterostructure PMOS device exhibits 4.5times enhancement in the drive current and transconductance (G_m) as compared to the homojunction planar device (Si_0.7Ge_0.3). This large enhancement can be attributed to several factors including Omega-gated nanowire structure, enhanced hole injection efficiency (due to valence band offset), and improved hole mobility (due to compressive strain and Ge enrichment in the nanowire channel).