Masao Ito

10-bit 50 MS/S 300 MW A/D converter using reference feed-forward architecture

This paper describes a 10-bit 50MS/s 300mW CMOS ADC employing time-interleaved, 4-stage pipelined configuration. To reduce power dissipation, Reference Feed-Forward architecture is introduced. In this architecture, resistive-load differential amplifiers (DifAMPs) are used between two pipline stages instead of high-gain high-speed amplifiers. The gain matching of the reference voltage with the internal signal range is achieved by a reference generator (RefGEN) having the same characteristics as a DAC/subtractor (DA/subt) circuit. The offset voltages of the DifAMPs are canncelled by the offset cancellation technique. The front-end sample/hold (S/H) circuit is eliminated to reduce power dissipation. By introducing high-speed comparators based on source follower and latch circuit into the 1st-stage A/D subconverter (ADSC), analog bandwidth is not degraded.