Yoshikazu Morooka

Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an experimental chip and an emulation motherboard mounting several SLDRAM emulation modules. The experimental chip is packaged and mounted on a conventional PCB module. The interface of the chip operates up to 600 Mb/s per pin with a 300 MHz clock.

An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only reaches /spl minus/0.6 V. HPC can pump without the threshold voltage (V/sub th/) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V/sub bb/ level lower than /spl minus/1.0 V is necessary to meet the limitations of the V/sub th/, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection. >

An adjustable output driver with a self-recovering Vpp generator for a 4M/spl times/16 DRAM

An adjustable output driver with a self-recovering Vpp generator for a 4 M/spl times/16 DRAM (dynamic random-access memory) is presented. Its driver characteristics can easily be changed between fast mode and slow mode in the assembly process. The driver with a small inductance load operates 2.5 ns faster in fast mode than in slow mode, and the driver in slow mode reduces the initial drive current and prevents ringing waveforms even with large inductance load. With a 5 pF capacitance load and 20 cm wire, the ringing amplitude in slow mode is reduced to 1/3 that of the fast mode. Users can choose the operation mode of the output driver according to their application. The self-recovering Vpp generators feed 16 output drivers and control the generator capacity according to the data pattern to supply the same amount of Vpp charge consumed by output drivers. The Vpp generator saves 3.9 mA on average at a 25 ns read cycle.

A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory

We propose a high speed and low power data transfer scheme for the wide internal data bus of an AS-Memory using the asynchronous compressed pulse width modulation (AC-PWM) technique and an automatic gain controlled (AGC) amplifier. The maximum bit rate per bus of AC-PWM increases by 12 times that of the conventional 100MHz data bus. The AGC amplifier achieves a fast data output while reducing by 1/3 the standby current. The proposed architecture is a key advance in the future development of AS-Memories.

Cell-plate-line and bit-line complementarily sensed (CBCS) architecture for ultra low-power non-destructive DRAMs

In order to develop very high density DRAMs, the reduction of memory-array current, accounting for over 80% of total chip current, must be given serious consideration. As the number of activated sense-amplifiers (SAs) increase, the amount of consumed charge on bit-lines (BLs) increases accordingly. This paper describes a novel circuit design, called Cell-Plate-Line and Bit-Line Complementarily Sensed (CBCS) Architecture. Only the selected SA of a whole array is activated, thereby reducing array read/write current to below 1% compared with conventional ones. Furthermore, refresh operation can easily be executed and the array refresh current is reduced to below 50% without loss of the read-out differential signal.

An efficient charge recycle and transfer pump circuit for low operating voltage DRAMs

An efficient Vpp generator with a charge recycle pump and a charge transfer pump have been proposed. The charge recycle operation can reduce the Vpp generating current by 38% without decreasing the Vpp supply current. The charge transfer operation enables the generation of the Vpp supply current at over the 2/spl middot/Vcc level. These techniques are highly effective in low voltage DRAMs.

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced.

A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory

We propose a high speed and low power data transfer scheme for the wide internal data bus of an AS-Memory using the asynchronous compressed pulse width modulation (AC-PWM) technique and an automatic gain controlled (AGC) amplifier. The maximum bit rate per bus of AC-PWM increases by 12 times that of the conventional 100MHz data bus. The AGC amplifier achieves a fast data output while reducing by 1/3 the standby current. The proposed architecture is a key advance in the future development of AS-Memories.