Paweł Tomaszewicz

Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs

The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.

The Influence of Functional Decomposition on Modern Digital Design Process

General functional decomposition has been gaining more and more importance in recent years. Though it is mainly perceived as a method of logic synthesis for the implementation of Boolean functions into FPGA-based architectures, it has found applications in many other fields of modern engineering and science. In this paper, an application of balanced functional decomposition in different tasks of modern digital designing is presented. The experimental results prove that functional decomposition as a method of synthesis can help implementing circuits in CPLD/FPGA architectures. It can also be efficiently used as a method for implementing FSMs in FPGAs with Embedded ROM Memory Blocks.

Embedded Damage Localization Subsystem Based on Elastic Wave Propagation

This article presents an embedded signal processing subsystem constituting a part of a whole structural health monitoring system (SHM). Typical SHM system is responsible for elastic wave generation and sensing, signal acquisition, and signal processing. Signal processing subsystem was designed with the aim of localizing damage utilizing elastic wave propagation in the interrogated structure. The embedded signal processing subsystem is realized in a field programmable gate array chip, which also implements a damage localization algorithm designed for creating damage maps that can indicate elastic wave reflection sites within the investigated structure. Elastic waves are generated and received using a prototype electronic system developed specially for this purpose. Piezoelectric transducers are arranged in networks with different geometrical configurations (strip, cross, and square). Elastic waves are excited by a five-cycle tone burst signal with carrier frequency of 220 kHz. The investigated structure is a simple isotropic panel made out of aluminum alloy. First, dispersion curves are computed on the basis of registered elastic wave signals. These are subsequently used in the damage localization process. The damage localization process utilizes the base antisymmetric A0 mode. This article presents results of experimental verification of the developed damage localization algorithm as well as results of damage localization by the embedded subsystem.

Virtualization Devices for Prototyping of Future Internet

In this paper we present three virtualization devices (Xen server, NetFPGA and EZ appliance) which have been used for implementation of data plane functionality in a Future Internet architecture, the IIP System. We give general description of these devices and present implementation of the IIP System node on each device.

Logic Synthesis Importance in FPGA-Based Designing of Image and Signal Processing Systems

General functional decomposition has been gaining more and more importance in recent years. Though it is mainly perceived as a method of logic synthesis for implementation of Boolean functions into FPGA-based architectures, it has found application in many other fields of modern engineering and science. In this paper, application of logic decomposition to efficient implementation of image and signal processing system in modern FPGA architectures is described. We have adapted an algorithm called Demain that can be used as a preprocessing tool in the FPGA synthesis flow. Wavelet filters are used to test Demain with Alteras Stratix device family and the experimental results are compared with those by Alteras Quartus tool. When Demain is used as a premapping processing, it shows 50% improvement in terms of the covered area by embedded memory blocks.

A notion of r-admissibility and its application in logic synthesis

Abstract This paper presents a theory for disjoint and non-disjoint multi-output Boolean function decomposition. This method is dedicated for FPGAs with embedded memory blocks (EMB). Proposed technique is an extension of known approach commonly used for LUT-based FPGA structures. A scheme for generating the set of bound variables that make the function decomposable is presented. Experiments that were carried out show significant area reduction.

Self-testing of S-compatible test units in user-programmed FPGAs

A method for the development of a test plan for BIST based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone. Logic cones that satisfy single-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. The number of test blocks corresponds to the number of test sessions. For the presented algorithm of computing logic cones, a tool was developed. The presented experimental results are used to develop heuristic rules that control the logic cone merging process.

Using Symbolic Functional Decomposition to Implement FSMs in Heterogenous FPGAs

This paper presents initial results of applying symbolic functional decomposition method to implementation of finite state machines in heterogenous FPGA structures. The results obtained with a prototypical academic tool art decomp are compared to traditional approaches, which use separate encoding and mapping steps.

Efficient Functional Decomposition Algorithm Based on Indexed Partition Calculus

This paper presents an efficient functional decomposition method based on the indexed partition calculus. The computational efficiency of indexed partition manipulation procedures allows performing multilevel logic synthesis for multi-output, not fully specified Boolean functions of large number of input variables. The presented results prove that the proposed approach can generate results of high quality.