Tae-Hyoung Kim

Antenna Ratio for Sum-Rate Maximization in Full-Duplex Large-Array Base Station with Half-Duplex Multiantenna Users

This paper analyzes the ratio of transmit antennas to receive antennas at the base station (BS) in full-duplex multiuser multiple-input-multiple-output (MU-MIMO) systems with large-array BS and half-duplex multiantenna users. We consider a full-duplex BS with a block diagonalization (BD) precoder for downlink transmission and a BD receive filter for uplink reception. We derive the approximated downlink sum-rate considering the inter-user interference, and the uplink sum-rate considering the self-interference (SI), for large numbers of BS antennas. Based on the analysis, we formulate an optimization problem in terms of the ratio of transmit antennas to receive antennas to maximize the sum-rate. The analysis shows that the antenna ratio for maximizing the sum rate converges to the ratio of downlink streams to uplink streams as the number of total BS antennas goes to infinity. Simulation results confirm the analysis and show that the BS using the derived antenna ratio in the full-duplex MU-MIMO system can achieve about a 10~20 b/s/Hz performance gain compared with the BS using an equal number of transmit and receive antennas.

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch

This paper describes memory interface circuits applicable to multi Gbit/s/pin chip-to-chip communication. To obtain the high linearity characteristics of the off-chip drivers (OCD) and the on-die terminators (ODT), a novel circuit structure is proposed. The linearity error of the designed OCD and ODT is 4.7% and 1.7% respectively when measured between 0.2V and 1V. The pull-up and pull-down impedance mismatch is reduced by adding a compensation impedance unit. The maximum pull-up and pulldown mismatch is 0.5 bit. An impedance update scheme without training sequence is designed to guarantee the signal integrity of the first data. The valid data window is 418ps at 2Gbit/s, Vref /spl plusmn/150mV. The proposed circuits are fabricated with 0.1/spl mu/m dual-oxide CMOS process technology.

Statistical Beamforming Based on Effective Channel Gain for Spatially Correlated Massive MIMO Systems

A statistical beamforming (SBF) scheme based on the effective channel gain (ECG) is proposed for spatially correlated massive multiple-input multiple-output systems. The proposed SBF scheme consists of outer and inner precoders. The outer precoder is designed to eliminate multiuser interference based on the correlation matrix of downlink channel. Then, according to the ECG defined as the squared inner product of the dedicated channel and an arbitrary precoding vector, the inner precoder is selected among the eigenvectors of the dedicated channel’s correlation matrix with the maximum ECG. Simulation results show that the proposed SBF scheme outperforms conventional schemes.

A High Resolution, Wide Range Digital Impedance Controller

This paper describes a digital impedance controller (DIC) for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23/spl Omega/ to 140/spl Omega/ with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is +2.26% with RQ ranging from 23/spl Omega/ to 53/spl Omega/ the same range covered by conventional scheme. High-resolution and wide range impedance control are implemented by using automatic gate voltage optimization. The data input valid window is 623ps at 0.75/spl plusmn/200mV and maximum eye open is 641mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface.

A high resolution, wide range digital impedance controller for high-speed SRAM interface

This paper describes a digital impedance controller (DIC) for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23/spl Omega/ to 140/spl Omega/ with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is +2.26% with RQ ranging from 23/spl Omega/ to 53/spl Omega/ the same range covered by conventional scheme. High-resolution and wide range impedance control are implemented by using automatic gate voltage optimization. The data input valid window is 623ps at 0.75/spl plusmn/200mV and maximum eye open is 641mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface.