Kwang-Jin Lee

Modeling and testing of faults in TCAMs

This paper proposes novel fault models for ternary content addressable memories (TCAMs) regarding both physical defects and functional fault models. Novel test algorithms which guarantee high fault coverage and small test length for detecting the faults in high density TCAM cell array is also proposed. The proposed TS−−T algorithm is suitable for detecting physical faults with compact test patterns and provides 92% fault coverage with small test length. Also, the proposed TM−−T algorithm makes it possible to detect various bridging faults among adjacent cells of high density CAMs. The test access time is (10 * l * 3 + 3 ) * write time and (12 * l * 3) * compare time in a n word by l bit TCAM.

A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops

This paper presents a digitally controlled oscillator (DCO) for high speed ADPLLs. The proposed DCO circuit has control codes of thermometer type, which can reduce jitters. Performance of the DCO is verified through a novel ADPLL. The ADPLL chip with the DCO was fabricated using a 0.18mum CMOS technology. The ADPLL has operation range between 520MHz and 1.5GHz and has 76ps peak-to-peak jitter at 668MHz

A Low Jitter ADPLL for Mobile Applications

This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type. Therefore, the DCO has small area and it has significantly small jitter when the control input is updated. The hierarchical DCO type with two loops makes it possible to have fine resolution and wide lock range. Functional verification and noise analysis of the ADPLL is performed by MATLAB simulink to improve design TAT (Turn-Around Time). And The ADPLL chip is in fabrication using a SEC 0.18 μm CMOS technology. The ADPLL has lock range between 520 MHz and 1.5 GHz and has peak-to-peak jitter 70 ps at 670 MHz.

Novel microfluidic chip generating mono-disperse core-shell microcapsules

In this paper, we propose a microfluidic chip to generate well-defined microcapsule. In order to make core-shell microcapsule, a simple design capable of 3-dimensional hydrodynamic focusing was embedded in the proposed microfluidic chip. Cell suspension is focused 3-dimensional hydrodynamic in microchannel by the hillock based geometries, and then the core-shell structure of alginate microcapsules with thin membrane can be clearly identified. The mouse embryonic carcinoma cell line, P19, was cultured in the capsules and spherical EB (more than 70 %) with strong compaction was successfully formed within 2 days.

A High Resolution, Wide Range Digital Impedance Controller

This paper describes a digital impedance controller (DIC) for high-speed signal interface. The proposed DIC provides the wide range impedance control covering from 23/spl Omega/ to 140/spl Omega/ with 3.29% maximum quantization error. The maximum quantization error of the proposed DIC is +2.26% with RQ ranging from 23/spl Omega/ to 53/spl Omega/ the same range covered by conventional scheme. High-resolution and wide range impedance control are implemented by using automatic gate voltage optimization. The data input valid window is 623ps at 0.75/spl plusmn/200mV and maximum eye open is 641mV meaning about 10% improvement at 1.5Gbps/pin DDR3 SRAM interface.