Tae Jong Lee

Stress-induced voiding in multi-level copper/low-k interconnects

Stress-induced voiding phenomenon in vias at different metallization layers was studied in details with stress temperatures ranging from 150/spl deg/C to 300/spl deg/C. At 1000-hour of stress migration (SM) test, the percentage change in the resistance showed that the thermally induced stress in the vias increased with increasing metallization layers. Furthermore, the vias at the edge of the wafer were more sensitive to the thermally induced stress than that at the center of the wafer. As such, more stress-induced damaged vias were observed at the upper metallization layers and at the edge of the wafer. These phenomena were attributed to the accumulated compressive stress experienced by the wafer with each increasing metallization layer and the poorer diffusion barrier coverage at the edge of the wafer due to the nature of physically vapor deposition (PVD) process. Some strategies such as the implementation of a resputtering step during the PVD process of the diffusion barrier layer and the design of dual-via interconnect were demonstrated to be effective in managing the stress-induced voiding effect in Cu interconnects. It was also proven that re-sputtering step during the PVD process of the diffusion barrier layer was necessary when Cu was integrated with dielectric of lower constant values because of its stronger dependency on process.

Stress migration reliability of wide Cu interconnects with gouging vias

Stress migration (SM) reliability of wide copper (Cu) interconnects with gouging vias was studied using a via chain structure stressed at temperatures ranging from 150/spl deg/C to 200/spl deg/C. After a 1000-hour SM test, via chain structures at the edge of the wafer were observed to have extremely high resistance due to the formation of stress-induced voids at the silicon nitride (Si/sub 3/N/sub 4/) cap/via interface around the perimeter of the gouging via and at the via bottom. One of the dominant causes for this phenomenon was attributed to the presence of process-induced weak points resulting from poor diffusion barrier layer coverage at the sidewall of the via bottom. In addition, a simulation model based on a three dimensional (3D) finite element analysis (FEA) was developed to study the stress distribution of a gouging via. The simulation results showed that high tensile stress was found at the Si/sub 3/N/sub 4/ cap/via interface around the perimeter of the gouging via. It is believed that at high temperature stressing, the presence of process-induced weak points, coupled with the high tensile stress, favor void nucleation. The steep stress gradient developed around the void vicinity after its nucleation was proposed to be the dominant driving force for subsequent vacancy accumulation and void growth extending beneath the gouging via, thus leading eventually to an open circuit. The effect of via gouging on the SM performance of Cu interconnects was also discussed.

Effects of low k film properties on electromigration performance

This paper will compare the reliability results of first-generation Carbon-doped low k dielectric film with a second-generation Carbon-doped film, developed to have a high mechanical strength (HMS) and improved toughness. The first-generation low k film possessed acceptable unit process results, but was found to have marginal electromigration (EM) performance due to cohesive failures that resulted in Cu extrusion at the anode end of lines. By replacing the first-generation film with the HMS film, EM test median time to fail was increased by a factor of more than two. This improvement was found to be due to increased film fracture toughness.