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Dive into the research topics where Randall Cher Liang Cha is active.

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Featured researches published by Randall Cher Liang Cha.


international symposium on plasma process induced damage | 2001

In-line plasma induced charging monitor for 0.15 /spl mu/m polysilicon gate etching

Daniel Chong; Won Jong Yoo; Ting Cheong Ang; Sang Yee Loong; Randall Cher Liang Cha; Pin Hian Lee; N. Layadi; Lap Chan; Alex See

Plasma induced charging damage from polysilicon gate etch was studied using both end-of-line polysilicon antenna test structures and in-line surface potential measurement (SPM) techniques. This study is performed on a 0.15 /spl mu/m gate patterning process using two different polysilicon etch chambers. In the study, the standard deviation and range of surface potentials obtained from the SPM technique show the same trend as those of threshold voltages obtained from polysilicon antenna test structures. The SPM technique could be used as an add-on method to antenna test structures for monitoring plasma induced charging damage.


Archive | 2000

Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant

Randall Cher Liang Cha; Tae Jong Lee; Alex See; Lap Chan; Chee Tee Chua


Archive | 2001

Dual silicon-on-insulator device wafer die

Randall Cher Liang Cha; Yeow Kheng Lim; Alex See; Tae Jong Lee; Wang Ling Goh


Archive | 2002

Method of fabricating variable length vertical transistors

Chew-Hoe Ang; Eng Hua Lim; Randall Cher Liang Cha; Jia Zhen Zheng; Elgin Quek; Mei Sheng Zhou; Daniel Yen


Archive | 2003

Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing

Chew Hoe Ang; Eng-Hua Lim; Randall Cher Liang Cha; Jia Zhen Zheng; Elgin Quek; Mei-Sheng Zhou; Daniel Yen


Archive | 2001

Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique

Randall Cher Liang Cha; Tae Jong Lee; Alex See; Lap Chan; Yeow Kheng Lim


Archive | 2001

Versatile copper-wiring layout design with low-k dielectric integration

Randall Cher Liang Cha; Alex See; Yeow Kheng Lim; Tae Jong Lee; Lap Chan


Archive | 2001

Method to fabricate RF inductors with minimum area

Randall Cher Liang Cha; Tae Jong Lee; Alex See; Lap Chan; Chua Chee Tee


Archive | 2001

Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance

Yeow Kheng Lim; Randall Cher Liang Cha; Alex See; Tae Jong Lee; Wang Ling Goh


Archive | 2001

Simplified method to reduce or eliminate STI oxide divots

Randall Cher Liang Cha; Tae Jong Lee; Alex See; Lap Chan; Yeow Kheng Lim

Collaboration


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Alex See

Chartered Semiconductor Manufacturing

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Lap Chan

Chartered Semiconductor Manufacturing

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Tae Jong Lee

Chartered Semiconductor Manufacturing

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Jia Zhen Zheng

Chartered Semiconductor Manufacturing

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Yeow Kheng Lim

Chartered Semiconductor Manufacturing

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Daniel Yen

Chartered Semiconductor Manufacturing

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Elgin Quek

Chartered Semiconductor Manufacturing

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Eng Hua Lim

Chartered Semiconductor Manufacturing

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Mei Sheng Zhou

Chartered Semiconductor Manufacturing

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Chew Hoe Ang

Chartered Semiconductor Manufacturing

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