Tae-yong Kim

Enhanced data retention of damascene-finFET DRAM with local channel implantation and fin surface orientation engineering

80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>10/sup 5/ endurance and good retention at 150/spl deg/C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.

Hot carrier generation and reliability of BT(body-tied)-Fin type SRAM cell transistors (W/sub fin/=20/spl sim/70 nm)

In this paper, we fabricated a BT-FinFET SRAM device with the smallest cell size of 0.46 /spl mu/m/sup 2/. And a hot carrier generation mechanism in the FinFET is thoroughly evaluated by measuring the I/sub sub/ of the BT-FinFET for various Si fin widths (20/spl sim/70 nm). For the first time, we revealed the mechanism of improved hot carrier immunity of sub 50 nm fin type MOSFETs.

Technology Breakthrough of Body-Tied FinFET for sub 50 nm NOR Flash Memory

We have achieved an optimal scheme for the practical application of body-tied FinFET for sub 50 nm NOR flash memory. Using this scheme, high program speed (Vt>8V@1mus) and low drain disturbance (DeltaVt=-0.1V@5ms) with a good reliability have been demonstrated. The effects of USC (ultra-shallow conformal) doping and SGHE (secondary generated hot electron) injection on program and drain disturbance characteristics of FinFET cells have been intensively studied. In addition, the (100) channel engineered body-tied FinFET shows manufacturable endurance characteristics

Improved post-cycling characteristic of FinFET NAND Flash

In this paper, SONOS type FinFET device has been fabricated and characterized for the NAND flash application. Pre- and post-cycling characteristics are mainly studied both for the FinFET and planar device, with respect to the memory cell performance and device reliability. It has been demonstrated that the performance improvement of the FinFET is maintained after cycling stress, and most importantly, the superior bake retention characteristic of FinFET device is observed after cycling stress compared to the planar device

Hf-silicate inter-poly dielectric technology for sub 70nm body tied FinFET flash memory

We report for the first time on 256Mb NOR-type body tied FinFET flash memory using Hf silicate IPD (inter poly dielectric) and compare with FinFET flash memory using traditional ONO IPD. An enlarged coupling ratio through Hf silicate IPD enhanced a CHEI (channel hot electron injection) programming speed and made the operation voltage down. And we could obtain a higher erasing speed resulted from HHI (hot hole injection) erase than that of F-N tunneling without degrading endurance characteristics.

The Vth controllability of 5nm body-tied CMOS FinFET

In this paper, we demonstrate a 5nm width body-tied CMOS finFET on bulk Si for the first time. Also the threshold voltage control of the 5nm finFET is shown by using channel and pocket doping profile optimization along the narrow active fin. The excellent performance of finFET such as an excellent subthreshold swing (SS), and drain induced barrier lowering (DIBL) characteristics were found. And the systemic analyses of electrical characteristics dependencies on the fin width were evaluated for various fin width (5 /spl sim/ 100nm).

Highly manufacturable 90 nm NOR flash technology with 0.081 /spl mu/m/sup 2/ cell size

A manufacturable 90 nm NOR Flash technology has been developed with extremely small cell size of 0.081/spl mu/m/sup 2/, which is the smallest cell size of NOR cell, for high density code storage memory featuring with low voltage operation. The small cell size of 0.081/spl mu/m/sup 2/ is successfully achieved with three key main technologies such as an advanced KrF lithography with off-axis illumination system, appropriate dielectric thin film and junction scaling and optimized oxidation encroachment of inter-poly oxide nitride oxide (ONO) and tunnel oxide.

Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor

Thanks to the combination of damascene gate and outer poly-Si sidewall spacer process, we have successfully fabricated twin silicon–oxide–nitride–oxide–silicon (SONOS) memory (TSM) transistors with 20-nm twin nitride storage nodes under an 80-nm gate. In terms of device manufacturability, the damascene gate process makes it possible to realize physically separated structure and the outer poly-Si sidewall spacer scheme contributes to realization of 20-nm long nitride storage node. Compared with conventional SONOS transistor, the fabricated TSM transistor maintains its threshold voltage margin between the forward and reverse reads down to 80-nm long gate. The TSM transistor also shows stable and reliable characteristics: up to 105 program/erase cycles endurance and fairly good bake retention at 150°C.