Eun Suk Cho

Enhanced data retention of damascene-finFET DRAM with local channel implantation and fin surface orientation engineering

80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

Growth of carbon nanotube field emitters on single strand carbon fiber: a linear electron source

The multi-stage effect has been revisited through growing carbon nanotube field emitters on single strand carbon fiber with a thickness of 11 µm. A prepared linear electron source exhibits a turn-on field as low as 0.4 V µm(-1) and an extremely high field enhancement factor of 19,300, when compared with those results from reference nanotube emitters grown on flat silicone wafer; 3.0 V µm(-1) and 2500, respectively. In addition, we introduce a novel method to grow nanotubes uniformly around the circumference of carbon fibers by using direct resistive heating on the continuously feeding carbon threads. These results open up not only a new path for synthesizing nanocomposites, but also offer an excellent linear electron source for special applications such as backlight units for liquid crystal displays and multi-array x-ray sources.

Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

We present a 2-bit/cell SONOS memory transistor and investigate its scalability and reliability beyond 50nm NVM technology. This new memory, which is implemented by the damascene gate and our newly developed outer sidewall spacer processes, shows not only stable 2-bit operation but also high reliabilities (>10/sup 5/ endurance and good retention at 150/spl deg/C) down to 80nm gate length that applies to next-generation NVM technology. In addition, dimensional effect (the lateral distance between two storage nodes) on the memory operation is reported to estimate the ultimate scaling limit of 2-bit/cell SONOS memory transistor.

Hot carrier generation and reliability of BT(body-tied)-Fin type SRAM cell transistors (W/sub fin/=20/spl sim/70 nm)

In this paper, we fabricated a BT-FinFET SRAM device with the smallest cell size of 0.46 /spl mu/m/sup 2/. And a hot carrier generation mechanism in the FinFET is thoroughly evaluated by measuring the I/sub sub/ of the BT-FinFET for various Si fin widths (20/spl sim/70 nm). For the first time, we revealed the mechanism of improved hot carrier immunity of sub 50 nm fin type MOSFETs.

Fin-type field-effect transistor NAND flash with nitride/silicon nanocrystal/nitride hybrid trap layer

The effects of trap layer on NAND flash performances have been described in this paper. In order to overcome the slower programming speed of the discrete trap memory than conventional floating-gate device, nitride and silicon nanocrystal have been assembled together so as to provide the higher trap density for the improved device performance. This hybrid trap layer technology has been applied to the fin-type field-effect transistor (FinFET) NAND flash, and the results show ~5 V of program/erase window with reasonable device reliabilities.

Technology Breakthrough of Body-Tied FinFET for sub 50 nm NOR Flash Memory

We have achieved an optimal scheme for the practical application of body-tied FinFET for sub 50 nm NOR flash memory. Using this scheme, high program speed (Vt>8V@1mus) and low drain disturbance (DeltaVt=-0.1V@5ms) with a good reliability have been demonstrated. The effects of USC (ultra-shallow conformal) doping and SGHE (secondary generated hot electron) injection on program and drain disturbance characteristics of FinFET cells have been intensively studied. In addition, the (100) channel engineered body-tied FinFET shows manufacturable endurance characteristics

Improved post-cycling characteristic of FinFET NAND Flash

In this paper, SONOS type FinFET device has been fabricated and characterized for the NAND flash application. Pre- and post-cycling characteristics are mainly studied both for the FinFET and planar device, with respect to the memory cell performance and device reliability. It has been demonstrated that the performance improvement of the FinFET is maintained after cycling stress, and most importantly, the superior bake retention characteristic of FinFET device is observed after cycling stress compared to the planar device