Junekyun Park

A process technology for 1 giga-bit DRAM

In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi/sub x/ gate, Self-Aligned Contact (SAG), and simple stack capacitor cell using (Ba,Sr)TiO/sub 3/ (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

Technology scaling on High-K & Metal-Gate FinFET BTI reliability

High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.

Interfacial Degradation Mechanism of Au/Al and Alloy/Al Bonds Under High Temperature Storage Test: Contamination, Epoxy Molding Compound, Wire and Bonding Strength

In this paper, the effects of Al pad contamination, epoxy molding compound [biphenyl (BP) and ortho-cresol novolac (OCN)] and wire (Au and alloy) on the propensity for the interfacial degradation of wire bond in a quad flap package under high temperature storage (HTS) tests at 125degC, 150degC, and 170degC are meticulously investigated. The interfacial degradation intends to be explicated in regards to change in surface morphology of Au-Al and alloy-Al intermetallic compound (IMC) and bonding strength as a function of HTS test. The combination of atomic force microscope and Auger electron spectrometry reveals that initial bonding strengths from wire pull and ball shear test decrease with increasing the thickness of contamination layer on Al pad, carbon and oxygen, and subsequent surface roughness. Indeed, the plasma exposure on Al pad prior to wire bonding enhances both mechanical bonding strengths up to 10% and 15%. It is found that the failure behaviors at 125degC are dissimilar to 150degC and 170degC. We first report that Sb diffused from the OCN exists at the intermetallics of Au-Al bonds, leading to rapidly deteriorate mechanical integrity. Furthermore, inductively coupled plasma mass spectrometry affirms that the OCN is a resource of Br. Above 150degC, the interdiffusion of Br and Sb from the OCN significantly impacts the integrity of Au-Al bonds. In turn, such physical degradation mechanism governed by Sb and Br can be linearly accelerated. It is also found that in the case of Au-Al bonds, the life time with the BP is much longer than that with the OCN under the given HTS tests due to less content of halogen ions. In contrast, neither Sb nor Br was found from the intermetallic layers of alloy-Al bond encapsulated with the OCN and BP. Thus, alloy-Al bonding strengths are intact even after longer stressing. With an alloy wire having Pd as an impurity, the growth kinetics of IMC fueled by Br and Sb seems to be sluggish, providing better reliability than Au wire. Obviously, lower flame retardants and higher are critical intrinsic material properties that should be taken into account when a new epoxy molding compound is introduced to pursue cost effectiveness without loosing reliability. Finally, upon painstaking work over a wide range of analyses herein, a quality affordable guideline for the selection of wire type associated with epoxy molding compound that can ensure the long-term reliability is presented in order to secure reliable supplyline management as well as package assembler.

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (tbd) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, tbd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter tbd than with DC at a lower frequency. This is attributed to hole trapping into IL as Vg is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer tbd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because Gm degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A BF/sub 3/ Plasma doping (PLAD) process has been utilized in source/drain/gate and shallow S/D extension for high performance 0.18 /spl mu/m pMOSFET. Gate oxide reliability, drain current, and transconductance of the pMOSFET with BF/sub 3/ PLAD are remarkably improved compared to those of BF/sub 2/ ion implanted devices. Cobalt salicide formation is also compatible with the plasma doped S/D junction.

Propensity of Copper Dendrite Growth on Subassembly Package Components Used in Quad Flat Package

Cu dendrite growth of quad flat package linked to epoxy molding compound (EMC), leadframe, and leadframe adhesive tape is comprehensively investigated. Cu dendrite grows particularly in the lead pitch smaller than les 130 mum covering with a leadframe tape, and in turn, it results in a resistive short. Such an appearance is attributed to test procedure of the precondition (30degC/60% relative humidity with 260-degC reflow) followed by biased stress test (125degC/1.95 V), which not only allows moisture condensation in the tape and but also provides bias between the leads. The influences of impurity in EMC and adhesive tape on dendrite formation are quantified with SEM-EDX, Auger electron spectrometry (AES), inductively coupled plasma-mass spectrometry (ICP-MS), and ICP-AES. As a result, the usage of nonhalide EMC can provide more reliable margin than that of larger lead spacing against Cu dendrite growth.

Reliability characterization of 10nm FinFET technology with multi-V T gate stack for low power and high performance

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-VTs through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different VT-types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.

Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster

The propensity of HCI and BTI degradation of HfSiON MOSFET on strained SiN-CESL performance booster is meticulously investigated. It is found that HCI and BTI lifetime of HfO based n/p MOSFET devices depend on hydrogen, initial Dit and plasma charging inherently related to the stress type of CESL fabricated with PECVD. In case for tensile CESL, n/p MOSFET devices far exceed reliability targets for both HCI and BTI. While compressive CESL on n/p MOSFET drastically depresses HCI and BTI lifetime.

Stress Evolution Related to Metal Routing in Submicron Multilevel Interconnects: Void and Extrusion

Failure mechanism of submicron multilevel interconnects encapsulated in a quad flat package subjected to high temperature operating life (HTOL) test under temperature and bias has been investigated. With the presence of void formation in the upper metal, Al extrudes from the lower metal to the adjacent metal lines leading to a fatal short failure. Void itself is not critical but later the growth of extrusion compromises the integrity and circuit reliability. Such a failure mechanism is explained with stress evolution on the metal routing associated with tensile stress imposed on the upper metal adhered to a thicker interlayer dielectric on certain points then relived with void formation that triggers compressive stress on the lower metal layer causing Al extrusion. For the purpose of verification, a new layout of the metal routing is committed and subjected to the HTOL. We found that the aspect ratio of the metal line significantly influences the integrity of submicron multilevel interconnects.