Nagisa Ishiura

Minimization of binary decision diagrams based on exchanges of variables

The authors present a novel exact algorithm and gradual improvement methods for minimizing binary decision diagrams (BDDs). In the exact minimization algorithm, the optimum order is searched by the exchanges of variables of BDDs based on the framework of the algorithm of S.J. Friedman and K.J. Supowit (1990). The use of the BDD representation of a given function and intermediate functions makes it possible to produce pruning into the method, which drastically reduces the computation cost. The authors succeeded in minimizing a 17-variable function by the use of the BDD representation of intermediate functions and the introduction of pruning. They also propose a greedy method and a simulated annealing method based on exchanges of two arbitrary variables, and a greedy method based on exchanges of adjacent m variables for m=3 and 4.<<ETX>>

Breadth-first manipulation of SBDD of Boolean functions for vector processing

Boolean function manipulators based on Shared Binary Decision Diagrams (SBDDs are utilized cation. We propose a high-speed algorithm of manipu- lating SBDDs, which can be used with a vector super- computer effectively. This proposed algorithm is imple- mented and evaluated on the vector supercomputer HI- TAC S-820/80. The vector acceleration ratio obtained is 14.3 in the best case. efficiently in various applications such as 1 esign verifi-

High-Speed Logic Simulation on Vector Processors

In this paper, we propose logic simulation techniques using vector processors, or supercomputers with pipeline architecture, as a new approach to accelerating simulation speed. In order to use vector processors efficiently, we have to tune up the coding scheme or the basic algorithms to be suitable for vector processing. We developed three types of new simulation techniques for vector processing, which are dedicated for (1) zero-delay simulation of combinational circuits, (2) zero-delay simulation of synchronous sequential circuits, and (3) simulation with delay consideration. The first two are based on the compiler-driven method and the last on the event-driven method. We implemented logic simulators based on the above techniques on the FACOM VP-100 and VP-200 at Kyoto University and on the HITAC S-810/20 at the University of Tokyo. The maximum performance is about 7.7 x 10 /sup 9/ gate-evaluations per second for combinational circuit simulation, 1.4 x 10 /sup 9/ gate-evaluations per second for sequential circuit simulation (on the VP-200), and 230 x 10 /sup 3/ events per second for timing simulation (on the S-810/20). These results are comparable to the performance of hardware simulation engines. Moreover, our techniques are so straightforward that we can implement them on most of the recent vector processors without serious modifications

Coded time-symbolic simulation using shared binary decision diagram

In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. We are concerned with simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. We encode the cases of possible delay values of each gate by binary values and simulate all the possible combinations of the delay values by means of symbolic simulation. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using a shared binary decision diagram (SBDD) as an internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.

Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor

An approach to accelerating fault simulation using a vector super computer is described and the zero-delay, two-valued fault simulation of gate-level combinational circuits is discussed. As a vector processor oriented simulation technique, an algorithm was developed that is based on the parallel fault simulation technique. In the technique, fault simulation can be accelerated (given that enough vector lengths can be obtained) to a maximum of 20 times faster using vector operations of a currently available vector computer by extending the processing unit from one word to multiple words. However, when fault simulation to generate or to evaluate test patterns is performed, enough vector length is not obtained or the computation time increases if large vector length is attempted because detected faults are dropped. In order to address the problems, a dynamic, two-dimensional, parallel fault simulation technique is proposed. In this technique, large vector length is obtained by utilizing both fault and pattern parallelism, and fault dropping is efficiently used to adjusting the two parallelism factors complementarily from pass to pass. The computation time is further reduced by combining this technique with selective tracing under the notion of multiple fault propagation. The experiments on the FACOM vector processor show that the simulation speed is accelerated by 10 to about 15 times through vectorization. >

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits

As a new approach for timing verification of logic circuits, we propose a new concept of time-symbolic simulation. While a conventional symbolic simulator treats signal values as logical expressions, a time-symbolic simulator treats time as algebraic expressions. In this paper, we describe algorithms for time-symbolic simulation, and its application to hazard detection and verification of asynchronous sequential circuits.

Probabilistic CTSS: analysis of timing error probability in asynchronous logic circuits

We propose a new technique of calculating timing error probabilities named probabilistic CTSS. We are concerned with timing verification of logic circuits consisting of gates whose delay values are uncertain but specified by their minimum and maximum values. This technique is based on coded time-symbolic simulation(CTSS), which was proposed in our previous work. Probabilistic CTSS calculates timing error probabilities closer to reality than a conventional method which fails to do the task because of reconvergences in the circuits.

Semantics of a Hardware Design Language for Japanese Standardization

We propose a new approach to define a formal semantics of a hardware design language (HDL) in Japanese LSI design language standardization project. Our approach is to separate the definition of semantics from simulators. Since the semantics includes nondeterminism, we can describe vagueness of circuit behavior such as dispersion of delays without linguistic ambiguity. We introduce a new computation model of hardware behaviour called NES (Nondeterministic Event Sequence) model. NES model is a very simple model of the computation in digital systems and provides an intuitive understanding of concurrent behaviour of HDL description without loss of mathematical strictness.

Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions

This paper presents an enhanced method of testing validity of arithmetic optimization of C compilers us- ing randomly generated programs. Its bug detection capability is improved over an existing method by 1) generating longer arithmetic expressions and 2) accommodating multiple expressions in test programs. Undefined behavior in long expressions is successfully eliminated by modifying problematic subexpressions during computation of expected values for the expressions. A new method for including floating point operations into compiler random testing is also proposed. Furthermore, an efficient method for minimizing error inducing test programs is presented, which utilizes binary search. Experimental results show that a random test system based on our method has higher bug detection capability than existing methods; it has detected more bugs than previous method in earlier versions of GCCs and has revealed new bugs in the latest versions of GCCs and LLVMs.

Fault simulation for multiple faults using shared BDD representation of fault sets

The authors propose a novel fault simulation technique for multiple faults. In order to handle a large number of multiple faults, sets of multiple faults are represented by Boolean functions, in which shared binary decision diagrams (BDDs) are used as an internal representation of Boolean functions. The authors also propose a fault dropping method, prime fault dropping, which is used efficiently to execute multiple fault simulation. The authors have succeeded in simulating 39 million double faults of a circuit of 2300 gates with about 20 Mbyte storage.<<ETX>>