Takahiro Ohnakado

21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)

This paper reports a 21.5-dBm power-handling 5-GHz transmit/receive CMOS switch utilizing the depletion-layer-extended transistor (DET), which possesses high effective substrate resistance and enables the voltage division effect of the stacked transistor configuration to work in the CMOS switch. Furthermore, low insertion losses of 0.95 and 1.44 dB are accomplished at 5 GHz in the transmit and receive modes, respectively, with the benefit of the insertion-loss improvement effects in the DET. At the same time, high isolations of more than 22 dB were obtained at 5 GHz in the transmit and receive modes with the adoption of the shunt/series type circuit.

21.5 dBm power-handling 5 GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with Depletion-layer-Extended Transistors (DETs)

This paper reports for the first time an over-20 dBm power-handling 5 GHz transmit/receive (T/R) CMOS switch. The Depletion-layer-Extended Transistor (DET), which possesses high effective substrate resistance, enables the voltage division effect of the stacked transistor configuration to work in CMOS, thus realizing this high power-handling capability. Furthermore, despite insertion-loss (I/sub L/) degradation due to double on-resistance with the stacked transistor configuration, a receive-mode I/sub L/ (I/sub L/@RX) of as low as 1.44 dB at 5 GHz is accomplished with the benefit of the I/sub L/ improvement effects in the DET, in addition to a very low transmit-mode I/sub L/ (I/sub L/@TX) of 0.95 dB at 5 GHz.

Device characteristics of 0.35 /spl mu/m P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-/spl mu/m-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 /spl mu/s/512 byte) and a low current consumption of less than 250 /spl mu/A were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10/sup 6/ program/erase cycles, and window narrowing and G/sub m/ degradation were found to be very small even after 10/sup 6/ cycles. It is thought that the BBHE injection point contributes to the G/sub m/ stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories.

Novel self-limiting program scheme utilizing N-channel select transistors in P-channel DINOR flash memory

This paper describes a novel self-limiting program scheme applying N-channel select transistors in the P-channel DINOR flash memory, which makes it possible to maintain the high programming throughput even for future lower-voltage flash memories. Using this scheme, programming stops automatically at the desired threshold voltage state without any conventional verify operations. Moreover, the width of the additional applied pulses is a very short 0.1 /spl mu/s and therefore it hardly degrades the programming speed at all. This novel scheme is expected to become a key technology for realization of the future, high-performance, lower-supply-voltage P-channel DINOR flash memory.

A 1.4 dB insertion-loss, 5 GHz transmit/receive switch utilizing novel depletion-layer-extended transistors (DETs) in 0.18 /spl mu/m CMOS process

A novel depletion-layer-extended transistor (DET) for the RF switch circuit is proposed in a CMOS process, which significantly reduces junction capacitance and increases GND-path resistance in the Si-substrate, with new impurity profiling. This transistor can be simultaneously formed with the conventional transistor with the addition of only one mask-step. By utilizing the DETs, a low 1.4 dB insertion-loss, 5 GHz transmit/receive switch in a 0.18 /spl mu/m CMOS process is realized.

1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the advantages of the P-channel DINOR (DIvided bit line NOR) flash memory, but also realizes the amplification of cell current, which is favorable for fast access operation.

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

A 0.8 dB insertion-loss, 23 dB isolation, 17.4 dBm power-handling, 5 GHz transmit/receive CMOS switch

The highest performance to date of any switch using a CMOS process, with a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

An Electrostatic-Discharge(ESD) Protection Device with Low Parasitic Capacitance Utilizing a Depletion-Layer-Extended Transistor(DET) for RF CMOS ICs

In this paper, an electrostatic-discharge (ESD) protection device for RF complementary metal oxide semiconductor (CMOS) ICs utilizing the Depletion-layer-Extended Transistor (DET) [rf1] is reported. The DET, which reduces the area component of junction capacitance by about 1/3, realizes an ESD protection device with low parasitic capacitance. With transmission line pulse (TLP) testing, the DET demonstrates about the same or higher ESD robustness than the conventional transistor. The junction capacitance of the proposed device for obtaining a failure current (It2) of 1–1.33 A in TLP testing, corresponding to a Human Body Model (HBM) tolerance of 2 kV, is estimated to be very low, less than 150 fF. The proposed ESD protection device is very promising for the realization of high-performance and highly reliable RF CMOS ICs.

Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory.