Kazuyuki Sugahara

A three-dimensional static RAM

A three-dimensional (3-D) 256-bit static random-access memory (RAM) with double active layers has been fabricated by using the laser recrystallization technique. Memory cells were located in a bottom active layer with an NMOS configuration and peripheral circuits were arranged in a top active layer with a CMOS configuration. Both active layers were connected by 112 via holes. The chip and cell sizes were 2.6 × 1.9 mm2and 50 × 70 µm2, respectively. The memory operation was observed with a supply voltage from 4 to 8 V. The shortest address access time of 42 ns was obtained at the supply voltage of 8 V.

SOI/SOI/Bulk-Si triple-level structure for three-dimensional devices

The fabrication procedure of the SOI/SOI/bulk-Si triple-level structure is developed by using the improved selective laser recrystallization technique and MOS LSI technology. The enlarged crystal stripes sandwiched by straight grain boundaries are produced on the planarized insulating film which overlies the device structure in bulk-Si, and also SOI/bulk-Si double-layered structure. The basic characteristics of MOSFETs in a triple-level structure are evaluated.

Orientation control of the silicon film on insulator by laser recrystallization

We have studied the influence of the growth direction and the solidification speed on crystal quality of the silicon‐on‐insulator (SOI) film by laser recrystallization. In a 〈100〉 direction on a {100} Si substrate, lateral epitaxial growth of single‐crystal regions from a seed extended as much as 1 mm. It was found that the crystalline orientation of the SOI film changes continuously from {100} toward {110}. These results indicated that the quality of the SOI film is strongly affected by the crystallographic arrangement of the growth front relative to the composition of {111} faceted planes. A new recrystallization method for large area SOI films was developed by stabilizing the growth front.

A 1.4 dB insertion-loss, 5 GHz transmit/receive switch utilizing novel depletion-layer-extended transistors (DETs) in 0.18 /spl mu/m CMOS process

A novel depletion-layer-extended transistor (DET) for the RF switch circuit is proposed in a CMOS process, which significantly reduces junction capacitance and increases GND-path resistance in the Si-substrate, with new impurity profiling. This transistor can be simultaneously formed with the conventional transistor with the addition of only one mask-step. By utilizing the DETs, a low 1.4 dB insertion-loss, 5 GHz transmit/receive switch in a 0.18 /spl mu/m CMOS process is realized.

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

Lateral impurity transport in silicon films on insulators during laser recrystallization

The lateral transport of dopants in silicon films on insulators during laser recrystallization is investigated. The dopants implanted locally in silicon films on insulators are found to be transported in the forward direction of the laser scan as well as the backward direction. Both transport lengths from the originally implanted region are measured as a function of the laser scan velocity. The transport mechanism is explained by taking into account a liquid phase diffusion and a segregation of impurities depending on the crystallization speed. The diffusion coefficients of (1.2±0.2)×10−4 and (1.3±0.4)×10−4 cm2/s for arsenic and boron, respectively, in molten silicon are obtained.

Topographical characteristics of recrystallized silicon films by scanning cw laser irradiation

Chemical vapor deposited polycrystalline silicon on insulating layer has been crystallized by scanning cw Ar laser irradiation. Recrystallized films have several features in their topographical characteristics. A ridge with periodic humps along the trace of the laser beam scan has been observed remarkably for films thicker than 0.7 μm. It is considered that the surface feature is due to movements of molten silicon during the laser irradiation. In the case of silicon islands recrystallized by laser irradiation after local oxidation of surrounding polycrystalline silicon, a slight depression of a silicon film at the starting side of the island for the laser beam scan and swell at the counter end have been formed. These phenomena are explained by a movement of a molten silicon hump as well as in the case of continuous films.

Evaluation of hot carrier effects in TFT by emission microscopy

Hot carrier degradation of p-channel polycrystalline silicon thin film transistors was investigated by emission microscopy. An automatic measurement system was developed for the evaluation of hot carrier degradation. In the system, the measurement of electrical characteristics and the monitoring of photoemission are done simultaneously. This system was used to identify the dominant mechanism of hot carrier degradation in thin-film transistors and to evaluate the effect of plasma hydrogenation on hot carrier degradation.<<ETX>>

Properties of a SiC Schottky Barrier Diode Fabricated with a Thin Substrate

One of the attractive methods to reduce the differential resistance of SiC devices is to make the thickness of a SiC substrate thinner [1]. Therefore, we fabricated SiC Schottky barrier diode (SBD) chips with a thickness below 150 μm and the properties of the SiC-SBD chips were measured. It was confirmed that the junction temperature of the thin SiC-SBD chips was decreased by the combination of the reduction in a thickness of the chip and the back side bonding of the chip using a material with high thermal conductivity. Moreover, it was confirmed that the potential of the thin SiC-SBD chip for the surge current capacity could be enhanced to combine the thin SiC-SBD chip with the back side bonding which has high thermal conductivity.

An Electrostatic-Discharge(ESD) Protection Device with Low Parasitic Capacitance Utilizing a Depletion-Layer-Extended Transistor(DET) for RF CMOS ICs

In this paper, an electrostatic-discharge (ESD) protection device for RF complementary metal oxide semiconductor (CMOS) ICs utilizing the Depletion-layer-Extended Transistor (DET) [rf1] is reported. The DET, which reduces the area component of junction capacitance by about 1/3, realizes an ESD protection device with low parasitic capacitance. With transmission line pulse (TLP) testing, the DET demonstrates about the same or higher ESD robustness than the conventional transistor. The junction capacitance of the proposed device for obtaining a failure current (It2) of 1–1.33 A in TLP testing, corresponding to a Human Body Model (HBM) tolerance of 2 kV, is estimated to be very low, less than 150 fF. The proposed ESD protection device is very promising for the realization of high-performance and highly reliable RF CMOS ICs.