Natsuo Ajika

Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell

A novel electron injection scheme for flash memory is proposed, where band-to-band tunneling induced hot electrons (BBHE) are employed in a P-channel cell. This proposed method ensures the realization of high program efficiency, high scalability and hot-hole-injection-free operation. We also demonstrate an application of the method to DINOR (DIvided bit-line NOR) program operation. An ultra-high-speed programming of 60 nsec/Byte can be achieved with a leakage current less than 1 mA by utilizing 512 Byte parallel programming. This new DINOR flash memory is shown to be the most promising for the realization of a low-voltage, high-performance and high-reliability flash memory of 64 Mbits and beyond.

A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure

A 3.6 mu m/sup 2/ 5 V only 16 Mb flash EEPROM cell was obtained using a simple stacked gate structure and a conventional 0.6 mu m CMOS process. A single 5 V power supply operation of the simple stacked gate cell was realized by optimizing the well impurity concentration and the drain structure and using a gate negative biased erasing operation. It is also shown that the gate negative biased erasing operation mode is very effective in improving the cell endurance characteristics.<<ETX>>

A quantitative analysis of stress induced excess current (SIEC) in SiO/sub 2/ films

The low-level stress induced excess current (SIEC) characteristics of 92 /spl Aring/ wet oxide are investigated in detail. As a result of the systematic investigations of the low-level E-J characteristics and the corresponding changes of net oxide charge, we have found that SIEC can be interpreted as electron tunneling processes into five kinds of different traps. As for the reproducible SIEC components, a quantitative analysis has been developed. By precisely modeling the trap assisted tunneling process, it has been shown that the E-J and t-J characteristics of the pretunneling region can be completely simulated as an electron tunneling process into the neutral trap. Using this analysis, it has been found that the local neutral trap density in bulk SiO/sub 2/ remains constant under the same hole fluence Qhole, regardless of the electric field strength during V/sub g/>0 FN stresses. In consequence, it has been concluded that the neutral trap has been created by holes injected into the oxide during the stresses.

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell. >

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 mu m*2.0 mu m and a chip size of 6.5 mm*18.4 mm were achieved using a simple stacked gate cell structure and 0.6- mu m CMOS process. >

A new decoding scheme and erase sequence for 5 V only sector erasable flash memory

The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase.<<ETX>>

New erase scheme for DINOR flash memory enhancing erase/write cycling endurance characteristics

New erase scheme for DINOR (Divided Bit Line NOR) flash memory is proposed and investigated, which utilizes substrate hot electron(SHE) injection instead of FN tunnel injection for erasure. Additional process or alteration of the cell structure is not needed to realize SHE erasure. The cell is formed in a triple well structure. The bottom n-well layer, which surrounds the p-well, is used as electron supply source in the SHE. By adopting SHE for erasure, the electric field required across the tunnel oxide was reduced to 1/4, compared with FN erasure. It needs less than 1 second for erasure, which is sufficient for DINOR operation. It is shown that V th window narrowing during erase/write cycling was significantly reduced by using SHE for erasure, as compared with using FN tunneling. The mechanism of enhanced erase/write cycling endurance is also examined.<<ETX>>

A novel process technology and cell structure for mega bit EEPROM

A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16 V in both write and erase operation, using Fowler-Nordheim electron tunneling between the floating gate and the n/sup +/ region. The endurance of the cell is greater than 100000 erase/write cycles. An SSTR cell with a capacitive coupling ratio of 0.83 and a cell area of 30.4 mu m/sup 2/ has been implemented in a 1-Mb EEPROM.<<ETX>>

Row-redundancy scheme for high-density flash memory

Flash memory is recognized as one of the key devices of personal digital assistant and other portable equipment. Rapid expansion of the market is expected because it is estimated that the cost of flash memory will eventually be lower than that of DRAM. However, to achieve low cost, a highly efficient redundancy scheme must be implemented for the chip. Although the same column redundancy scheme used in DRAM and SRAM can be applied to flash memory, conventional row redundancy in which defective word lines are replaced by spare word lines is not suitable. In flash memory, all memory cells in the erase block must be programmed before the erase pulse is applied to the memory array to avoid over-erasure. If the replaced word line is shorted to the adjacent word line, memory cells on the defective word line cannot be programmed even if the replaced word line is selected because the word line is grounded through the adjacent word line.<<ETX>>

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0- mu m triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 mu m*8 mu m, and the chip is 7.73 mm*11.83 mm. The device is configured as either 128 k*8 or 64 k*16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.<<ETX>>