Takamitsu Nagai

Development of voltage contrast defect inspection technique for line monitoring 300mm ULSI hp90 logic contact layer

We had investigated the voltage contrast defect inspection technique using 300mm wafer size hp 90nm contact logic devices for line-monitoring implementation. The investigation was carried out on the basis of signal intensity analysis of the voltage contrast image in relation to landing energy, charge control voltage, beam current, diffusion types and charge quantities of wafer surface. As a results, it was determined that voltage contrast was not only dependent on the balance between the surface potential of the Si-oxide surface due to charge-up and surface potential of contact, but it was also dependent on the balance between the surface potential of contact and each diffusion layer. By adjusting the parameters of landing energy, charge control voltage and beam current on basis of D.O.E. (Design of an experiment using 3 x 3 parameters) for contact logic device inspection, we were able to optimize EB condition for the best sensitivity, namely, 100% capture rate, 20% nuisance rate, and the best signal intensity of voltage contrast defect. In the next step, we attempted to reduce the nuisance rate. We adopted on i-ADC (In-line automated defect mode clas sification) function, namely, a nuisance filter. By adjusting the parameters of intensity, polarity, and size of nuisance defects, we were able to confirm the reduction of the nuisance rate less than 0.5%. Using this technique, the inspection of 300mm wafer size hp 90nm contact logic production wafer for line monitoring was carried out. In the case of line monitoring, the required inspection performances were robustness between different lots, and fast-throughput. On the basis of the results of the inspection, we confirmed that a nuisance rate of less than 0.5% between different lots could be achieved by using these techniques (optimized EB condition and nuisance filter).Robustness of inspection between different lots was achieved. In a further step, we attempted to achieve fast throughput. The target inspection time for line monitoring was set at about 1 hour /wafer. By adjusting the parameters of pixel size and sampling of die row on the wafer, we obtained optimized condition with fast throughput. We confirmed that an inspection time of about 1 hour /wafer could be achieved with 25% sampling of die row. The effectiveness of line-monitoring for inspection of electric failure mode, which can not be detected by the optical inspection system, was confirmed. The contribution to fast ramp-up is as follows. The shorter turnaround time (TAT) of electrical contact failure mode analysis, which can be reduced by about 1 month compared with the time required for E-Test, was confirmed.

Development of Sample Planning for Wafer Defect Inspection

Sample planning for wafer defect inspection is a critical issue for reducing total cost. It is important to develop a cost‐effective sampling plan. In the present study, using three parameters (gain, coefficient of gain variation, and payback period), an optimized sampling plan has been identified by principal component analysis. In particular, a robust sampling plan can be evaluated in terms of a coefficient of gain variation and a cost‐effective sampling plan can be evaluated in terms of both gain and the payback period. This indicates that the optimal sampling plan must be designed from both economic and technical viewpoints to reduce the total inspection cost.