Takashi Onizawa

A proposal of new concept milli-second annealing: Flexibly-shaped-pulse flash lamp annealing (FSP-FLA) for fabrication of ultra shallow junction with improvement of metal gate high-k CMOS performance

We propose the suitable milli-second annealing (MSA) for metal/high-k device performance and ultra-shallow-junction (USJ) fabrication: flexibly-shaped-pulse flash lamp annealing (FSP-FLA). The conventional FLA treatment on metal/high-k device degrades its effective electron mobility (mueff) and bias temperature instability (BTI) characteristics. A recovery annealing (RA) treatment after FLA is most effective to recover those degradations. However, the annealing after dopant activation causes deactivation and diffusion. The FSP-FLA allowed us sub-10-milli-second annealing after activation FLA; it realizes high BTI reliability and high mueff without deactivation and diffusion.

Ultra-uniform threshold voltage in SONOS-type non-volatile memory with novel charge trap layer formed by plasma nitridation

We have proposed a new method to prepare thin nitrogen-based charge trap layer for scaled-down SONOS with thin EOT (<12nm). Devices employing an ONO prepared by the newly proposed method, a N2-plasma treated base oxide topped by an HTO, showed unprecedented Vth uniformity, carrier localization and good retention characteristics. An overall comparison with Si3N 4-SONOS is given. They also offer excellent transistor characteristics (high on-current and low Vth), making them ideal for future scaled low-voltage embedded applications with fast readout

Improving Junction Uniformity and Quality with Optimized Diffusion-less Annealing

Comparisons between B, Ge+B and B18H22 implantations for pSDE were made. With Flash only the localized individual Xe-lamps signature was clearly detected by PLi and Rs measurements. Adding a spike first RTA anneal dramatically improved the global and local micro uniformity variation by 2-3x with either a 1000degC or 900degC spike 1st anneal. The highest quality B junctions were achieved with B18H22 for all annealing conditions as verified by PLi value and junction leakage current.

Advanced Flash Lamp Annealing technology for 22nm and further device

Idea of a very short time annealing technology has evaluated in 1980s. Engineers tried to use Flash lamp, laser or some other lamps [1]. In 1990s, W-halogen lamp annealing replaced furnace annealing in activation and silicidation process. Thermal budget has reduced from minutes to seconds. Eager for Milli-second Annealing (MSA) really came out in 2000s. Since dopant diffusion and an activation ratio have been considered to be more critical obstacle in scaled down microstructure devices, FLA activation technology came into spotlight again [2–9]. A 65nm device was a first product which used Flash Lamp Annealing (FLA) in manufacturing. Today, milli-second process has become an indispensable method in device manufacturing. But device generation keeps proceeding 45nm, 32nm and so on. Furthermore, a new material like high-k/metal is selected as a latest device material. Difficulty in MSA for 32 and 22 generation devices is reported recently.

Multi-functional annealing using flexibly-shaped-pulse flash lamp annealing (FSP-FLA) for high-k/metal gated CMOS devices

We have presented functional annealing data using the FSP-FLA, together with some examples of the multi-functionality. First, we showed that the FSP-FLA can control thermal budget whilst sustaining high dopant activation, recovering crystalline defects, and controlling thermal diffusion length. Secondly, by combining impulses from conventional FLA and the trapezoidal pulse of the FSP-FLA, we can improve BTI lifetime and μeff, without degrading Rs-Xj characteristics. In addition, we showed the FSP-FLA pulse for preheat control. Therefore, we have a high confidence that FLA has evolved to the 2nd generation with the FSP-FLA system and it will be a main-stream annealing method for scaled high-k/metal gated devices in the near future.

Improvement of Metal/High-k Device Performance by 40-Milli-Second Flash Lamp Annealing by using Flexibly-Shaped-Pulse Technology

Abstract We improved TaSiN/HfSiON stacked device performance by using ultra-long-pulse flash-lamp-annealing (FLA) using flexibly-shaped-pulse (FSP) technology [1]. A 40 ms FSP-FLA recovers degradation of its effective electron mobility (μeff), and bias temperature instability (BTI) lifetime which induced by conventional FLA treatment on metal/high-k device. And it achieves higher device performance than that of sRTA by high activation and low diffusion. Introduction The fabrication of ultra-shallow-junction (USJ) by using milli-second-anneal (MSA) is a topic for 32-nm-node CMOS device and beyond. Recently, the impacts of MSA such as FLA or laser anneal on CMOS device performance have been reported [1-4]. The conventional FLA (~ 1 ms) on metal/high-k induces its μeff and BTI degradation caused by interfacial reaction and/or wafer-wrapping during rapid and high temperature annealing [1, 2]. In this study, to resolve those problems, we used low-power and ultra-long-pulse (15, 25, 40 ms) FLA using FSP technology. Results and discussions I. USJ performance for ultra-long-pulse FSP-FLA First, dopant diffusion and activation were investigated by using bare wafer. The dopant ion implantation (I/I) conditions are (a) As 2 keV 10 cm or (b) B 0.5 keV 10 cm with Ge pre-amorphous implantation (PAI). Those I/I conditions simulated source and drain extensions for (a) NMOS and (b) PMOS, respectively. After the I/I, 1000C sRTA or conventional FLA (0.8 ms) or ultra-long-pulse FSP-FLA (15, 25, 40 ms) was performed. Figure 1 shows schematic pulse-shape comparison of conventional FLA (0.8 ms) and FSP-FLA (15, 25, 40 ms) used in this work. Lower and longer trapezoidal shape pulse FLA was performed by FSP-FLA. The sheet resistance (Rs) of the samples is shown in Fig. 2. Both As and B, FLA and FSP-FLA show lower Rs than that of sRTA. The Rs of 40 ms FSP-FLA are higher than those of 25ms. Little dopant deactivation seems to be occurred. The thermal wave (T.W.) signal for the samples is shown in Fig. 3. A low T.W. generally means low crystal defects. The T.W. signals of 25 and 40 ms FSP-FLA are lower than that of conventional FLA. This indicates I/I damage was recovered by longer FLA pulse. In the case of B with PAI, both Rs and T.W. of 15 ms FSP-FLA sample are enormous values. It indicates < 15 ms FSP-FLA could not recover surface PAI layer completely [5]. Figure 4 shows SIMS profiles of (a) As and (b) B for the samples annealed with sRTA, FLA and 40 ms FSP-FLA, respectively. And Fig. 5 shows Rs vs. junction depth (Xj) estimated from the SIMS profile. Both of Rs and Xj of 40 ms FSP-FLA take a value between conventional FLA and sRTA. II. Metal/high-k device performance Next, we investigated the impacts of FLA condition on metal/high-k devices. Figure 6 shows gate first process flow of TaSiN/HfSiON stacks. The activation annealing was performed by 1000C sRTA or conventional FLA (0.8 ms) or 15 ~ 40 ms FSP-FLA. For the all samples, FLA (0.8 ms) after extension I/I was performed to gain high activated extension. Figure 7 shows threshold voltage (Vth) roll-off for the samples. The roll-off of 40 ms FSP-FLA shows middle profile between sRTA and FLA that reflects dopant diffusion value. Figure 8 shows Ion Ioff characteristics for the samples. The Ion at Ioff = 100 nA/um for FLA and 40 ms FSP-FLA are +1.7 and +4.8% higher than that of sRTA, respectively. The highest Ion value for 40 ms FSP-FLA is caused by high dopant activation with μeff improvement. The μeff of the samples at 0.5 MV of gate electric field is shown in Fig. 9. The μeff is improved by longer FLA pulse. And the μeff of the 40 ms FSP-FLA sample achieves comparable to that of sRTA. The improvement of μeff seems to be caused by reduction of coulomb scattering. The reduction of electron trapping sites is investigated by PBTI (Fig. 10). The PBTI lifetime also improved with longer FLA pulse. It indicates that the electron trapping sites formed during extension FLA were recovered by long-time thermal treatment such as sRTA or 40 ms FSP-FLA. Therefore the 40 ms FSP-FLA sample showed improved μeff and PBTI lifetime. Figure 11 shows junction leakage (JL) for the all samples. The JL is reduced with FLA pulse becoming longer, too. The recovery of crystal defect and little dopant diffusion reduce the JL. 3. Conclusions Table I show USJ and device performances compared with sRTA. A conventional FLA and long-pulse FSP-FLA achieves higher dopant activation with lower diffusion than that of sRTA. As FLA pulse becoming longer, μeff and PBTI are improved, and the JL is decreased. In this study, 40 ms FSP-FLA show highest Ion because of high dopant activation with μeff improvement. A Further lengthen FLA pulse is sure to lead more improvement of BTI and reduction of JL for metal/high-k device. Acknowledgement The authors thank DAINIPPON SCREEN MFG. Co., LTD for FSP-FLA processing. References [1] T. Onizawa et al., to be presented in VLSI 2008. [2] P. Kalra et al., IEDM, p. 353 (2007). [3] T. Hoffmann et al., IWJT, p. 137 (2007). [4] A. Shima, et al., VLSI Tech. Dig., p. 174 (2004). [5] S. Kato et al., IWJT, p. 143 (2007) Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008,

Study of Ultra-shallow Junctions Formed by Flash Lamp Annealing to Reveal Dopant Activation Phenomenon

We studied the characteristics of ultra-shallow junctions (USJ) formed by flash lamp annealing (FLA) to reveal the nature of the dopant activation. A pre-amorphized layer is effective in activating dopants in FLA. End-of-range (EOR) defects remain close to amorphous/crystal (a/c) interface. FLA with low lamp power results in the amorphous layer remaining in the surface. Sb is highly activated, compared to As. These phenomena exhibit a correspondence with the activation during solid-phase epitaxial regrowth (SPER), where dopants are activated in a thermal non-equilibrium condition. Therefore, we conclude that FLA is a form of SPER, employing high temperatures and short (mili-second) times. The high temperature in FLA achieves higher dopant activation than obtained in SPER, whilst eliminating shortcomings found with SPER.

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on Bias Temperature Instability and Gate Dielectric Breakdown of HfSiON MOSFETs

We investigated the influences of gate metals (n+/p+ poly-Si, Ni silicide (NiSi), Ni3Si) on the time dependent dielectric breakdown (TDDB) reliability and negative/positive bias temperature instability (NBTI/PBTI) of phase-controlled Ni-full-silicide (Ni-FUSI)/HfSiON/SiO 2 FETs. The TDDB reliability of NiSi-electrode n-FETs was comparable to that of n+-poly-Si-electrode n-FETs. However, further Ni enriching of the electrode to Ni3Si degraded the reliability. A degradation of the base SiO2 layer seems to have been responsible for this. A higher compressive strain was observed for the Ni3Si sample, which may have caused the degradation of the bottom SiO2. In contrast, the TDDB reliability of p-FETs improved much by using Ni3Si. We attribute this improvement to the lower cathode energy and/or the absence of boron in the gate electrode. The PBTI of the n-FETs was negligible and was not degraded by Ni enrichment of the gate electrode and additional annealing, suggesting that HfSiON was stable against the Ni-FUSI process. The threshold voltage (VT) shift in NBTI of p-FETs did not depend much on the gate materials. The major component of the V T shift in NBTI, however, was changed by Ni enriching from the generation of interface traps to the trapping of holes by the HfSiON bulk

Impact of Crystalline Phase of Ni-Full-Silicide Gate Electrode on TDDB Reliability of HfSiON Gate Stacks

We investigated the influences of gate metals (poly-Si, NiSi, Ni 3Si) on the time dependent dielectric breakdown (TDDB) reliability of phase-controlled Ni-full-silicide/HfSiON n-FETs. The TDDB reliability of the NiSi-electrode FETs was comparable to that of poly-Si-electrode FETs. However, the reliability was degraded by further Ni-enriching to Ni3Si. We presume that the degradation of the base SiO2 layer is responsible for this. We do not relate the TDDB degradation to Ni diffusion into the insulator, but rather to the strain that is higher in Ni3Si samples

Anomalous behavior in the dependence of carrier activation on implant dose for extremely shallow source/drain extensions activated by flash lamp annealing

We investigated the influence of extremely high doping concentrations on the sheet resistance of ion implants annealed by FLA. As the implant depth was ultra-shallow and the amount of dopant atoms high, the concentration of dopant near the surface was exceedingly high, above the solid solubility limit, resulting in high Rs. The cause of this is mainly due to the formation of clusters, which was confirmed by calculation and experimental data. The clustering was occurred during the preheating process before the Xe-lamp flash irradiation.